1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2019-2022, Intel Corporation. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #ifndef AGX_PINMUX_H 8*91f16700Schasinglulu #define AGX_PINMUX_H 9*91f16700Schasinglulu 10*91f16700Schasinglulu #define AGX_PINMUX_BASE 0xffd13000 11*91f16700Schasinglulu #define AGX_PINMUX_PIN0SEL (AGX_PINMUX_BASE + 0x000) 12*91f16700Schasinglulu #define AGX_PINMUX_IO0CTRL (AGX_PINMUX_BASE + 0x130) 13*91f16700Schasinglulu #define AGX_PINMUX_EMAC0_USEFPGA (AGX_PINMUX_BASE + 0x300) 14*91f16700Schasinglulu #define AGX_PINMUX_EMAC1_USEFPGA (AGX_PINMUX_BASE + 0x304) 15*91f16700Schasinglulu #define AGX_PINMUX_EMAC2_USEFPGA (AGX_PINMUX_BASE + 0x308) 16*91f16700Schasinglulu #define AGX_PINMUX_NAND_USEFPGA (AGX_PINMUX_BASE + 0x320) 17*91f16700Schasinglulu #define AGX_PINMUX_SPIM0_USEFPGA (AGX_PINMUX_BASE + 0x328) 18*91f16700Schasinglulu #define AGX_PINMUX_SPIM1_USEFPGA (AGX_PINMUX_BASE + 0x32c) 19*91f16700Schasinglulu #define AGX_PINMUX_SDMMC_USEFPGA (AGX_PINMUX_BASE + 0x354) 20*91f16700Schasinglulu #define AGX_PINMUX_IO0_DELAY (AGX_PINMUX_BASE + 0x400) 21*91f16700Schasinglulu 22*91f16700Schasinglulu #define AGX_PINMUX_NAND_USEFPGA_VAL BIT(4) 23*91f16700Schasinglulu #define AGX_PINMUX_SDMMC_USEFPGA_VAL BIT(8) 24*91f16700Schasinglulu #define AGX_PINMUX_SPIM0_USEFPGA_VAL BIT(16) 25*91f16700Schasinglulu #define AGX_PINMUX_SPIM1_USEFPGA_VAL BIT(24) 26*91f16700Schasinglulu #define AGX_PINMUX_EMAC0_USEFPGA_VAL BIT(0) 27*91f16700Schasinglulu #define AGX_PINMUX_EMAC1_USEFPGA_VAL BIT(8) 28*91f16700Schasinglulu #define AGX_PINMUX_EMAC2_USEFPGA_VAL BIT(16) 29*91f16700Schasinglulu 30*91f16700Schasinglulu #include "socfpga_handoff.h" 31*91f16700Schasinglulu 32*91f16700Schasinglulu void config_pinmux(handoff *handoff); 33*91f16700Schasinglulu 34*91f16700Schasinglulu #endif 35*91f16700Schasinglulu 36