1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright 2023 NXP 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu #include <stdbool.h> 7*91f16700Schasinglulu 8*91f16700Schasinglulu #include <platform_def.h> 9*91f16700Schasinglulu #include <pwr_ctrl.h> 10*91f16700Schasinglulu 11*91f16700Schasinglulu /*Do the necessary GPC, SRC, BLK_CTRL_S init */ 12*91f16700Schasinglulu void pwr_sys_init(void) 13*91f16700Schasinglulu { 14*91f16700Schasinglulu unsigned int cpu; 15*91f16700Schasinglulu 16*91f16700Schasinglulu /* 17*91f16700Schasinglulu * Assigned A55 cluster to 3, m33 to 2, A55 CORE0 & CORE1 to 0/1. 18*91f16700Schasinglulu * domain0/1 only used for trigger LPM of themselves. A55 cluster & M33's 19*91f16700Schasinglulu * domain assignment should be align with the TRDC DID. 20*91f16700Schasinglulu */ 21*91f16700Schasinglulu gpc_assign_domains(0x3102); 22*91f16700Schasinglulu 23*91f16700Schasinglulu /* CA55 core0/1 config */ 24*91f16700Schasinglulu for (cpu = CPU_A55C0; cpu <= CPU_A55_PLAT; cpu++) { 25*91f16700Schasinglulu /* clear the cpu sleep hold */ 26*91f16700Schasinglulu gpc_clear_cpu_sleep_hold(cpu); 27*91f16700Schasinglulu /* use gic wakeup source by default */ 28*91f16700Schasinglulu gpc_select_wakeup_gic(cpu); 29*91f16700Schasinglulu /* 30*91f16700Schasinglulu * Ignore A55 core0/1's LPM trigger for system sleep. 31*91f16700Schasinglulu * normally, for A55 side, only the A55 cluster(plat) 32*91f16700Schasinglulu * domain will be used to trigger the system wide low 33*91f16700Schasinglulu * power mode transition. 34*91f16700Schasinglulu */ 35*91f16700Schasinglulu if (cpu != CPU_A55_PLAT) { 36*91f16700Schasinglulu gpc_force_cpu_suspend(cpu); 37*91f16700Schasinglulu } 38*91f16700Schasinglulu } 39*91f16700Schasinglulu 40*91f16700Schasinglulu /* boot core(A55C0) */ 41*91f16700Schasinglulu src_mem_lpm_en(SRC_A55P0_MEM, MEM_OFF); 42*91f16700Schasinglulu /* For A55 core, only need to be on in RUN mode */ 43*91f16700Schasinglulu src_mix_set_lpm(SRC_A55C0, 0x0, CM_MODE_WAIT); 44*91f16700Schasinglulu /* whitelist: 0x1 for domain 0 only */ 45*91f16700Schasinglulu src_authen_config(SRC_A55C0, 0x1, 0x1); 46*91f16700Schasinglulu 47*91f16700Schasinglulu /* A55 cluster */ 48*91f16700Schasinglulu gpc_select_wakeup_gic(CPU_A55_PLAT); 49*91f16700Schasinglulu gpc_clear_cpu_sleep_hold(CPU_A55_PLAT); 50*91f16700Schasinglulu 51*91f16700Schasinglulu /* SCU MEM must be OFF when A55 PLAT OFF */ 52*91f16700Schasinglulu src_mem_lpm_en(SRC_A55_SCU_MEM, MEM_OFF); 53*91f16700Schasinglulu /* L3 memory in retention by default */ 54*91f16700Schasinglulu src_mem_lpm_en(SRC_A55_L3_MEM, MEM_RETN); 55*91f16700Schasinglulu 56*91f16700Schasinglulu src_mix_set_lpm(SRC_A55P, 0x3, 0x1); 57*91f16700Schasinglulu /* whitelist: 0x8 for domain 3 only */ 58*91f16700Schasinglulu src_authen_config(SRC_A55P, 0x8, 0x1); 59*91f16700Schasinglulu 60*91f16700Schasinglulu /* enable the HW LP handshake between S401 & A55 cluster */ 61*91f16700Schasinglulu mmio_setbits_32(BLK_CTRL_S_BASE + HW_LP_HANDHSK, BIT(5)); 62*91f16700Schasinglulu } 63*91f16700Schasinglulu 64