1*91f16700Schasinglulu# 2*91f16700Schasinglulu# Copyright 2022-2023 NXP 3*91f16700Schasinglulu# 4*91f16700Schasinglulu# SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu# 6*91f16700Schasinglulu 7*91f16700SchasingluluPLAT_INCLUDES := -Iplat/imx/common/include \ 8*91f16700Schasinglulu -Iplat/imx/imx93/include \ 9*91f16700Schasinglulu# Translation tables library 10*91f16700Schasingluluinclude lib/xlat_tables_v2/xlat_tables.mk 11*91f16700Schasinglulu 12*91f16700SchasingluluGICV3_SUPPORT_GIC600 := 1 13*91f16700Schasinglulu 14*91f16700Schasinglulu# Include GICv3 driver files 15*91f16700Schasingluluinclude drivers/arm/gic/v3/gicv3.mk 16*91f16700Schasinglulu 17*91f16700SchasingluluIMX_GIC_SOURCES := ${GICV3_SOURCES} \ 18*91f16700Schasinglulu plat/common/plat_gicv3.c \ 19*91f16700Schasinglulu plat/common/plat_psci_common.c \ 20*91f16700Schasinglulu plat/imx/common/plat_imx8_gic.c 21*91f16700Schasinglulu 22*91f16700SchasingluluBL31_SOURCES += plat/common/aarch64/crash_console_helpers.S \ 23*91f16700Schasinglulu plat/imx/imx93/aarch64/plat_helpers.S \ 24*91f16700Schasinglulu plat/imx/imx93/plat_topology.c \ 25*91f16700Schasinglulu plat/imx/common/lpuart_console.S \ 26*91f16700Schasinglulu plat/imx/imx93/trdc.c \ 27*91f16700Schasinglulu plat/imx/imx93/pwr_ctrl.c \ 28*91f16700Schasinglulu plat/imx/imx93/imx93_bl31_setup.c \ 29*91f16700Schasinglulu plat/imx/imx93/imx93_psci.c \ 30*91f16700Schasinglulu lib/cpus/aarch64/cortex_a55.S \ 31*91f16700Schasinglulu drivers/delay_timer/delay_timer.c \ 32*91f16700Schasinglulu drivers/delay_timer/generic_delay_timer.c \ 33*91f16700Schasinglulu drivers/nxp/trdc/imx_trdc.c \ 34*91f16700Schasinglulu ${IMX_GIC_SOURCES} \ 35*91f16700Schasinglulu ${XLAT_TABLES_LIB_SRCS} 36*91f16700Schasinglulu 37*91f16700SchasingluluRESET_TO_BL31 := 1 38*91f16700SchasingluluHW_ASSISTED_COHERENCY := 1 39*91f16700SchasingluluUSE_COHERENT_MEM := 0 40*91f16700SchasingluluPROGRAMMABLE_RESET_ADDRESS := 1 41*91f16700SchasingluluCOLD_BOOT_SINGLE_CPU := 1 42*91f16700Schasinglulu 43*91f16700SchasingluluBL32_BASE ?= 0x96000000 44*91f16700SchasingluluBL32_SIZE ?= 0x02000000 45*91f16700Schasinglulu$(eval $(call add_define,BL32_BASE)) 46*91f16700Schasinglulu$(eval $(call add_define,BL32_SIZE)) 47