1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright 2022-2023 NXP 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #include <arch.h> 8*91f16700Schasinglulu #include <arch_helpers.h> 9*91f16700Schasinglulu #include <plat/common/platform.h> 10*91f16700Schasinglulu 11*91f16700Schasinglulu const unsigned char imx_power_domain_tree_desc[] = { 12*91f16700Schasinglulu PWR_DOMAIN_AT_MAX_LVL, 13*91f16700Schasinglulu PLATFORM_CLUSTER_COUNT, 14*91f16700Schasinglulu PLATFORM_CLUSTER0_CORE_COUNT, 15*91f16700Schasinglulu }; 16*91f16700Schasinglulu 17*91f16700Schasinglulu const unsigned char *plat_get_power_domain_tree_desc(void) 18*91f16700Schasinglulu { 19*91f16700Schasinglulu return imx_power_domain_tree_desc; 20*91f16700Schasinglulu } 21*91f16700Schasinglulu 22*91f16700Schasinglulu /* 23*91f16700Schasinglulu * Only one cluster is planned for i.MX9 family, no need 24*91f16700Schasinglulu * to consider the cluster id 25*91f16700Schasinglulu */ 26*91f16700Schasinglulu int plat_core_pos_by_mpidr(u_register_t mpidr) 27*91f16700Schasinglulu { 28*91f16700Schasinglulu unsigned int cpu_id; 29*91f16700Schasinglulu 30*91f16700Schasinglulu mpidr &= MPIDR_AFFINITY_MASK; 31*91f16700Schasinglulu 32*91f16700Schasinglulu if (mpidr & ~(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK)) { 33*91f16700Schasinglulu return -1; 34*91f16700Schasinglulu } 35*91f16700Schasinglulu 36*91f16700Schasinglulu cpu_id = MPIDR_AFFLVL1_VAL(mpidr); 37*91f16700Schasinglulu 38*91f16700Schasinglulu return cpu_id; 39*91f16700Schasinglulu } 40