1*91f16700Schasinglulu/* 2*91f16700Schasinglulu * Copyright 2022-2023 NXP 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu#include <asm_macros.S> 8*91f16700Schasinglulu#include <cortex_a55.h> 9*91f16700Schasinglulu 10*91f16700Schasinglulu#include <platform_def.h> 11*91f16700Schasinglulu 12*91f16700Schasinglulu .globl plat_is_my_cpu_primary 13*91f16700Schasinglulu .globl plat_my_core_pos 14*91f16700Schasinglulu .globl plat_calc_core_pos 15*91f16700Schasinglulu .globl platform_mem_init 16*91f16700Schasinglulu 17*91f16700Schasinglulu /* ------------------------------------------------------ 18*91f16700Schasinglulu * Helper macro that reads the part number of the current 19*91f16700Schasinglulu * CPU and jumps to the given label if it matches the CPU 20*91f16700Schasinglulu * MIDR provided. 21*91f16700Schasinglulu * 22*91f16700Schasinglulu * Clobbers x0. 23*91f16700Schasinglulu * ------------------------------------------------------ 24*91f16700Schasinglulu */ 25*91f16700Schasinglulu .macro jump_if_cpu_midr _cpu_midr, _label 26*91f16700Schasinglulu 27*91f16700Schasinglulu mrs x0, midr_el1 28*91f16700Schasinglulu ubfx x0, x0, MIDR_PN_SHIFT, #12 29*91f16700Schasinglulu cmp w0, #((\_cpu_midr >> MIDR_PN_SHIFT) & MIDR_PN_MASK) 30*91f16700Schasinglulu b.eq \_label 31*91f16700Schasinglulu 32*91f16700Schasinglulu .endm 33*91f16700Schasinglulu 34*91f16700Schasinglulu /* ---------------------------------------------- 35*91f16700Schasinglulu * unsigned int plat_is_my_cpu_primary(void); 36*91f16700Schasinglulu * This function checks if this is the primary CPU 37*91f16700Schasinglulu * ---------------------------------------------- 38*91f16700Schasinglulu */ 39*91f16700Schasinglulufunc plat_is_my_cpu_primary 40*91f16700Schasinglulu mrs x0, mpidr_el1 41*91f16700Schasinglulu mov_imm x1, MPIDR_AFFINITY_MASK 42*91f16700Schasinglulu and x0, x0, x1 43*91f16700Schasinglulu cmp x0, #PLAT_PRIMARY_CPU 44*91f16700Schasinglulu cset x0, eq 45*91f16700Schasinglulu ret 46*91f16700Schasingluluendfunc plat_is_my_cpu_primary 47*91f16700Schasinglulu 48*91f16700Schasinglulu /* ---------------------------------------------- 49*91f16700Schasinglulu * unsigned int plat_my_core_pos(void) 50*91f16700Schasinglulu * This function uses the plat_calc_core_pos() 51*91f16700Schasinglulu * to get the index of the calling CPU. 52*91f16700Schasinglulu * ---------------------------------------------- 53*91f16700Schasinglulu */ 54*91f16700Schasinglulufunc plat_my_core_pos 55*91f16700Schasinglulu mrs x0, mpidr_el1 56*91f16700Schasinglulu mov x1, #MPIDR_AFFLVL_MASK 57*91f16700Schasinglulu and x0, x1, x0, lsr #MPIDR_AFF1_SHIFT 58*91f16700Schasinglulu ret 59*91f16700Schasingluluendfunc plat_my_core_pos 60*91f16700Schasinglulu 61*91f16700Schasinglulu /* 62*91f16700Schasinglulu * unsigned int plat_calc_core_pos(uint64_t mpidr) 63*91f16700Schasinglulu * helper function to calculate the core position. 64*91f16700Schasinglulu * With this function. 65*91f16700Schasinglulu */ 66*91f16700Schasinglulufunc plat_calc_core_pos 67*91f16700Schasinglulu mov x1, #MPIDR_AFFLVL_MASK 68*91f16700Schasinglulu and x0, x1, x0, lsr #MPIDR_AFF1_SHIFT 69*91f16700Schasinglulu ret 70*91f16700Schasingluluendfunc plat_calc_core_pos 71*91f16700Schasinglulu 72*91f16700Schasinglulufunc platform_mem_init 73*91f16700Schasinglulu ret 74*91f16700Schasingluluendfunc platform_mem_init 75