1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #ifndef PLATFORM_DEF_H 8*91f16700Schasinglulu #define PLATFORM_DEF_H 9*91f16700Schasinglulu 10*91f16700Schasinglulu #include <lib/utils_def.h> 11*91f16700Schasinglulu 12*91f16700Schasinglulu #define PLATFORM_LINKER_FORMAT "elf64-littleaarch64" 13*91f16700Schasinglulu #define PLATFORM_LINKER_ARCH aarch64 14*91f16700Schasinglulu 15*91f16700Schasinglulu #define PLATFORM_STACK_SIZE 0x400 16*91f16700Schasinglulu #define CACHE_WRITEBACK_GRANULE 64 17*91f16700Schasinglulu 18*91f16700Schasinglulu #define PLAT_PRIMARY_CPU U(0x0) 19*91f16700Schasinglulu #define PLATFORM_MAX_CPU_PER_CLUSTER U(4) 20*91f16700Schasinglulu #define PLATFORM_CLUSTER_COUNT U(1) 21*91f16700Schasinglulu #define PLATFORM_CORE_COUNT U(4) 22*91f16700Schasinglulu #define PLATFORM_CLUSTER0_CORE_COUNT U(4) 23*91f16700Schasinglulu #define PLATFORM_CLUSTER1_CORE_COUNT U(0) 24*91f16700Schasinglulu 25*91f16700Schasinglulu #define PWR_DOMAIN_AT_MAX_LVL U(1) 26*91f16700Schasinglulu #define PLAT_MAX_PWR_LVL U(2) 27*91f16700Schasinglulu #define PLAT_MAX_OFF_STATE U(2) 28*91f16700Schasinglulu #define PLAT_MAX_RET_STATE U(1) 29*91f16700Schasinglulu 30*91f16700Schasinglulu #define BL31_BASE 0x80000000 31*91f16700Schasinglulu #define BL31_LIMIT 0x80020000 32*91f16700Schasinglulu 33*91f16700Schasinglulu #define PLAT_VIRT_ADDR_SPACE_SIZE (1ull << 32) 34*91f16700Schasinglulu #define PLAT_PHY_ADDR_SPACE_SIZE (1ull << 32) 35*91f16700Schasinglulu 36*91f16700Schasinglulu #define MAX_XLAT_TABLES 8 37*91f16700Schasinglulu #define MAX_MMAP_REGIONS 8 38*91f16700Schasinglulu 39*91f16700Schasinglulu #define PLAT_GICD_BASE 0x51a00000 40*91f16700Schasinglulu #define PLAT_GICR_BASE 0x51b00000 41*91f16700Schasinglulu 42*91f16700Schasinglulu #if defined(IMX_USE_UART0) 43*91f16700Schasinglulu #define IMX_BOOT_UART_BASE 0x5a060000 44*91f16700Schasinglulu #elif defined(IMX_USE_UART1) 45*91f16700Schasinglulu #define IMX_BOOT_UART_BASE 0x5a070000 46*91f16700Schasinglulu #elif defined(IMX_USE_UART3) 47*91f16700Schasinglulu #define IMX_BOOT_UART_BASE 0x5a090000 48*91f16700Schasinglulu #else 49*91f16700Schasinglulu #error "Provide proper UART configuration in IMX_DEBUG_UART" 50*91f16700Schasinglulu #endif 51*91f16700Schasinglulu 52*91f16700Schasinglulu #define IMX_BOOT_UART_BAUDRATE 115200 53*91f16700Schasinglulu #define IMX_BOOT_UART_CLK_IN_HZ 24000000 54*91f16700Schasinglulu #define PLAT_CRASH_UART_BASE IMX_BOOT_UART_BASE 55*91f16700Schasinglulu #define PLAT__CRASH_UART_CLK_IN_HZ 24000000 56*91f16700Schasinglulu #define IMX_CONSOLE_BAUDRATE 115200 57*91f16700Schasinglulu #define SC_IPC_BASE 0x5d1b0000 58*91f16700Schasinglulu #define IMX_GPT0_LPCG_BASE 0x5d540000 59*91f16700Schasinglulu #define IMX_GPT0_BASE 0x5d140000 60*91f16700Schasinglulu #define IMX_WUP_IRQSTR_BASE 0x51090000 61*91f16700Schasinglulu #define IMX_REG_BASE 0x50000000 62*91f16700Schasinglulu #define IMX_REG_SIZE 0x10000000 63*91f16700Schasinglulu 64*91f16700Schasinglulu #define COUNTER_FREQUENCY 8000000 65*91f16700Schasinglulu 66*91f16700Schasinglulu /* non-secure u-boot base */ 67*91f16700Schasinglulu #define PLAT_NS_IMAGE_OFFSET 0x80020000 68*91f16700Schasinglulu #define DEBUG_CONSOLE_A35 DEBUG_CONSOLE 69*91f16700Schasinglulu 70*91f16700Schasinglulu #endif /* PLATFORM_DEF_H */ 71