1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2019-2022 NXP. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #ifndef IMX_RDC_H 8*91f16700Schasinglulu #define IMX_RDC_H 9*91f16700Schasinglulu 10*91f16700Schasinglulu #include <lib/utils_def.h> 11*91f16700Schasinglulu 12*91f16700Schasinglulu #include <imx_sec_def.h> 13*91f16700Schasinglulu #include <platform_def.h> 14*91f16700Schasinglulu 15*91f16700Schasinglulu #define MDAn(x) (IMX_RDC_BASE + 0x200 + (x) * 4) 16*91f16700Schasinglulu #define PDAPn(x) (IMX_RDC_BASE + 0x400 + (x) * 4) 17*91f16700Schasinglulu #define MRSAn(x) (IMX_RDC_BASE + 0x800 + (x) * 0x10) 18*91f16700Schasinglulu #define MREAn(x) (IMX_RDC_BASE + 0x804 + (x) * 0x10) 19*91f16700Schasinglulu #define MRCn(x) (IMX_RDC_BASE + 0x808 + (x) * 0x10) 20*91f16700Schasinglulu 21*91f16700Schasinglulu #define LCK BIT(31) 22*91f16700Schasinglulu #define SREQ BIT(30) 23*91f16700Schasinglulu #define ENA BIT(30) 24*91f16700Schasinglulu 25*91f16700Schasinglulu #define DID0 U(0x0) 26*91f16700Schasinglulu #define DID1 U(0x1) 27*91f16700Schasinglulu #define DID2 U(0x2) 28*91f16700Schasinglulu #define DID3 U(0x3) 29*91f16700Schasinglulu 30*91f16700Schasinglulu #define D3R BIT(7) 31*91f16700Schasinglulu #define D3W BIT(6) 32*91f16700Schasinglulu #define D2R BIT(5) 33*91f16700Schasinglulu #define D2W BIT(4) 34*91f16700Schasinglulu #define D1R BIT(3) 35*91f16700Schasinglulu #define D1W BIT(2) 36*91f16700Schasinglulu #define D0R BIT(1) 37*91f16700Schasinglulu #define D0W BIT(0) 38*91f16700Schasinglulu 39*91f16700Schasinglulu union rdc_setting { 40*91f16700Schasinglulu uint32_t rdc_mda; /* Master Domain Assignment */ 41*91f16700Schasinglulu uint32_t rdc_pdap; /* Peripheral Domain Access Permissions */ 42*91f16700Schasinglulu uint32_t rdc_mem_region[3]; /* Memory Region Access Control */ 43*91f16700Schasinglulu }; 44*91f16700Schasinglulu 45*91f16700Schasinglulu enum rdc_type { 46*91f16700Schasinglulu RDC_INVALID, 47*91f16700Schasinglulu RDC_MDA, 48*91f16700Schasinglulu RDC_PDAP, 49*91f16700Schasinglulu RDC_MEM_REGION, 50*91f16700Schasinglulu }; 51*91f16700Schasinglulu 52*91f16700Schasinglulu struct imx_rdc_cfg { 53*91f16700Schasinglulu enum rdc_type type; /* config type Master, Peripheral or Memory region */ 54*91f16700Schasinglulu int index; 55*91f16700Schasinglulu union rdc_setting setting; 56*91f16700Schasinglulu }; 57*91f16700Schasinglulu 58*91f16700Schasinglulu #define RDC_MDAn(i, mda) \ 59*91f16700Schasinglulu {RDC_MDA, (i), .setting.rdc_mda = (mda), } 60*91f16700Schasinglulu #define RDC_PDAPn(i, pdap) \ 61*91f16700Schasinglulu {RDC_PDAP, (i), .setting.rdc_pdap = (pdap), } 62*91f16700Schasinglulu 63*91f16700Schasinglulu #define RDC_MEM_REGIONn(i, msa, mea, mrc) \ 64*91f16700Schasinglulu { RDC_MEM_REGION, (i), \ 65*91f16700Schasinglulu .setting.rdc_mem_region[0] = (msa), \ 66*91f16700Schasinglulu .setting.rdc_mem_region[1] = (mea), \ 67*91f16700Schasinglulu .setting.rdc_mem_region[2] = (mrc), \ 68*91f16700Schasinglulu } 69*91f16700Schasinglulu 70*91f16700Schasinglulu void imx_rdc_init(const struct imx_rdc_cfg *cfg); 71*91f16700Schasinglulu 72*91f16700Schasinglulu #endif /* IMX_RDC_H */ 73*91f16700Schasinglulu 74