1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #ifndef IMX8M_PSCI_H 8*91f16700Schasinglulu #define IMX8M_PSCI_H 9*91f16700Schasinglulu 10*91f16700Schasinglulu #define CORE_PWR_STATE(state) ((state)->pwr_domain_state[MPIDR_AFFLVL0]) 11*91f16700Schasinglulu #define CLUSTER_PWR_STATE(state) ((state)->pwr_domain_state[MPIDR_AFFLVL1]) 12*91f16700Schasinglulu #define SYSTEM_PWR_STATE(state) ((state)->pwr_domain_state[PLAT_MAX_PWR_LVL]) 13*91f16700Schasinglulu 14*91f16700Schasinglulu int imx_pwr_domain_on(u_register_t mpidr); 15*91f16700Schasinglulu void imx_pwr_domain_on_finish(const psci_power_state_t *target_state); 16*91f16700Schasinglulu void imx_pwr_domain_off(const psci_power_state_t *target_state); 17*91f16700Schasinglulu int imx_validate_ns_entrypoint(uintptr_t ns_entrypoint); 18*91f16700Schasinglulu void imx_cpu_standby(plat_local_state_t cpu_state); 19*91f16700Schasinglulu void imx_domain_suspend(const psci_power_state_t *target_state); 20*91f16700Schasinglulu void imx_domain_suspend_finish(const psci_power_state_t *target_state); 21*91f16700Schasinglulu void __dead2 imx_pwr_domain_pwr_down_wfi(const psci_power_state_t *target_state); 22*91f16700Schasinglulu int imx_system_reset2(int is_vendor, int reset_type, u_register_t cookie); 23*91f16700Schasinglulu 24*91f16700Schasinglulu #endif /* IMX8M_PSCI_H */ 25