1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2018-2023, ARM Limited and Contributors. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #ifndef IMX8M_GPC_H 8*91f16700Schasinglulu #define IMX8M_GPC_H 9*91f16700Schasinglulu 10*91f16700Schasinglulu #include <gpc_reg.h> 11*91f16700Schasinglulu 12*91f16700Schasinglulu /* helper macro */ 13*91f16700Schasinglulu #define A53_LPM_MASK U(0xF) 14*91f16700Schasinglulu #define A53_LPM_WAIT U(0x5) 15*91f16700Schasinglulu #define A53_LPM_STOP U(0xA) 16*91f16700Schasinglulu #define LPM_MODE(local_state) ((local_state) == PLAT_WAIT_RET_STATE ? A53_LPM_WAIT : A53_LPM_STOP) 17*91f16700Schasinglulu 18*91f16700Schasinglulu #define DSM_MODE_MASK BIT(31) 19*91f16700Schasinglulu #define CORE_WKUP_FROM_GIC (IRQ_SRC_C0 | IRQ_SRC_C1 | IRQ_SRC_C2 | IRQ_SRC_C3) 20*91f16700Schasinglulu #define A53_CORE_WUP_SRC(core_id) (1 << ((core_id) < 2 ? 28 + (core_id) : 22 + (core_id) - 2)) 21*91f16700Schasinglulu #define COREx_PGC_PCR(core_id) (0x800 + (core_id) * 0x40) 22*91f16700Schasinglulu #define COREx_WFI_PDN(core_id) (1 << ((core_id) < 2 ? (core_id) * 2 : ((core_id) - 2) * 2 + 16)) 23*91f16700Schasinglulu #define COREx_IRQ_WUP(core_id) ((core_id) < 2 ? (1 << ((core_id) * 2 + 8)) : (1 << ((core_id) * 2 + 20))) 24*91f16700Schasinglulu #define COREx_LPM_PUP(core_id) ((core_id) < 2 ? (1 << ((core_id) * 2 + 9)) : (1 << ((core_id) * 2 + 21))) 25*91f16700Schasinglulu #define SLTx_CFG(n) ((SLT0_CFG + ((n) * 4))) 26*91f16700Schasinglulu #define SLT_COREx_PUP(core_id) (0x2 << ((core_id) * 2)) 27*91f16700Schasinglulu #define SLT_COREx_PUP_ACK(core_id) ((core_id) < 2 ? (1 << ((core_id) + 16)) : (1 << ((core_id) + 27))) 28*91f16700Schasinglulu 29*91f16700Schasinglulu #define IMR_MASK_ALL 0xffffffff 30*91f16700Schasinglulu 31*91f16700Schasinglulu #define IMX_PD_DOMAIN(name, on) \ 32*91f16700Schasinglulu { \ 33*91f16700Schasinglulu .pwr_req = name##_PWR_REQ, \ 34*91f16700Schasinglulu .pgc_offset = name##_PGC, \ 35*91f16700Schasinglulu .need_sync = false, \ 36*91f16700Schasinglulu .always_on = (on), \ 37*91f16700Schasinglulu } 38*91f16700Schasinglulu 39*91f16700Schasinglulu #define IMX_MIX_DOMAIN(name, on) \ 40*91f16700Schasinglulu { \ 41*91f16700Schasinglulu .pwr_req = name##_PWR_REQ, \ 42*91f16700Schasinglulu .pgc_offset = name##_PGC, \ 43*91f16700Schasinglulu .adb400_sync = name##_ADB400_SYNC, \ 44*91f16700Schasinglulu .adb400_ack = name##_ADB400_ACK, \ 45*91f16700Schasinglulu .need_sync = true, \ 46*91f16700Schasinglulu .always_on = (on), \ 47*91f16700Schasinglulu } 48*91f16700Schasinglulu 49*91f16700Schasinglulu struct imx_pwr_domain { 50*91f16700Schasinglulu uint32_t pwr_req; 51*91f16700Schasinglulu uint32_t adb400_sync; 52*91f16700Schasinglulu uint32_t adb400_ack; 53*91f16700Schasinglulu uint32_t pgc_offset; 54*91f16700Schasinglulu bool need_sync; 55*91f16700Schasinglulu bool always_on; 56*91f16700Schasinglulu }; 57*91f16700Schasinglulu 58*91f16700Schasinglulu struct pll_override { 59*91f16700Schasinglulu uint32_t reg; 60*91f16700Schasinglulu uint32_t override_mask; 61*91f16700Schasinglulu }; 62*91f16700Schasinglulu 63*91f16700Schasinglulu DECLARE_BAKERY_LOCK(gpc_lock); 64*91f16700Schasinglulu 65*91f16700Schasinglulu /* function declare */ 66*91f16700Schasinglulu void imx_gpc_init(void); 67*91f16700Schasinglulu void imx_set_cpu_secure_entry(unsigned int core_index, uintptr_t sec_entrypoint); 68*91f16700Schasinglulu void imx_set_cpu_pwr_off(unsigned int core_index); 69*91f16700Schasinglulu void imx_set_cpu_pwr_on(unsigned int core_index); 70*91f16700Schasinglulu void imx_set_cpu_lpm(unsigned int core_index, bool pdn); 71*91f16700Schasinglulu void imx_set_cluster_standby(bool retention); 72*91f16700Schasinglulu void imx_set_cluster_powerdown(unsigned int last_core, uint8_t power_state); 73*91f16700Schasinglulu void imx_noc_slot_config(bool pdn); 74*91f16700Schasinglulu void imx_set_sys_wakeup(unsigned int last_core, bool pdn); 75*91f16700Schasinglulu void imx_set_sys_lpm(unsigned last_core, bool retention); 76*91f16700Schasinglulu void imx_set_rbc_count(void); 77*91f16700Schasinglulu void imx_clear_rbc_count(void); 78*91f16700Schasinglulu void imx_anamix_override(bool enter); 79*91f16700Schasinglulu void imx_gpc_pm_domain_enable(uint32_t domain_id, bool on); 80*91f16700Schasinglulu 81*91f16700Schasinglulu #if defined(PLAT_imx8mq) 82*91f16700Schasinglulu void imx_gpc_set_a53_core_awake(uint32_t core_id); 83*91f16700Schasinglulu void imx_gpc_core_wake(uint32_t cpumask); 84*91f16700Schasinglulu #endif 85*91f16700Schasinglulu 86*91f16700Schasinglulu #endif /*IMX8M_GPC_H */ 87