1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright 2019-2023 NXP 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #ifndef DRAM_H 8*91f16700Schasinglulu #define DRAM_H 9*91f16700Schasinglulu 10*91f16700Schasinglulu #include <assert.h> 11*91f16700Schasinglulu 12*91f16700Schasinglulu #include <arch_helpers.h> 13*91f16700Schasinglulu #include <lib/utils_def.h> 14*91f16700Schasinglulu 15*91f16700Schasinglulu #include <ddrc.h> 16*91f16700Schasinglulu #include <platform_def.h> 17*91f16700Schasinglulu 18*91f16700Schasinglulu #define DDRC_LPDDR4 BIT(5) 19*91f16700Schasinglulu #define DDRC_DDR4 BIT(4) 20*91f16700Schasinglulu #define DDRC_DDR3L BIT(0) 21*91f16700Schasinglulu #define DDR_TYPE_MASK U(0x3f) 22*91f16700Schasinglulu #define ACTIVE_RANK_MASK U(0x3) 23*91f16700Schasinglulu #define DDRC_ACTIVE_ONE_RANK U(0x1) 24*91f16700Schasinglulu #define DDRC_ACTIVE_TWO_RANK U(0x2) 25*91f16700Schasinglulu 26*91f16700Schasinglulu #define MR12 U(12) 27*91f16700Schasinglulu #define MR14 U(14) 28*91f16700Schasinglulu 29*91f16700Schasinglulu #define MAX_FSP_NUM U(3) 30*91f16700Schasinglulu 31*91f16700Schasinglulu /* reg & config param */ 32*91f16700Schasinglulu struct dram_cfg_param { 33*91f16700Schasinglulu unsigned int reg; 34*91f16700Schasinglulu unsigned int val; 35*91f16700Schasinglulu }; 36*91f16700Schasinglulu 37*91f16700Schasinglulu struct dram_timing_info { 38*91f16700Schasinglulu /* umctl2 config */ 39*91f16700Schasinglulu struct dram_cfg_param *ddrc_cfg; 40*91f16700Schasinglulu unsigned int ddrc_cfg_num; 41*91f16700Schasinglulu /* ddrphy config */ 42*91f16700Schasinglulu struct dram_cfg_param *ddrphy_cfg; 43*91f16700Schasinglulu unsigned int ddrphy_cfg_num; 44*91f16700Schasinglulu /* ddr fsp train info */ 45*91f16700Schasinglulu struct dram_fsp_msg *fsp_msg; 46*91f16700Schasinglulu unsigned int fsp_msg_num; 47*91f16700Schasinglulu /* ddr phy trained CSR */ 48*91f16700Schasinglulu struct dram_cfg_param *ddrphy_trained_csr; 49*91f16700Schasinglulu unsigned int ddrphy_trained_csr_num; 50*91f16700Schasinglulu /* ddr phy PIE */ 51*91f16700Schasinglulu struct dram_cfg_param *ddrphy_pie; 52*91f16700Schasinglulu unsigned int ddrphy_pie_num; 53*91f16700Schasinglulu /* initialized fsp table */ 54*91f16700Schasinglulu unsigned int fsp_table[4]; 55*91f16700Schasinglulu }; 56*91f16700Schasinglulu 57*91f16700Schasinglulu struct dram_info { 58*91f16700Schasinglulu int dram_type; 59*91f16700Schasinglulu unsigned int num_rank; 60*91f16700Schasinglulu uint32_t num_fsp; 61*91f16700Schasinglulu int current_fsp; 62*91f16700Schasinglulu int boot_fsp; 63*91f16700Schasinglulu bool bypass_mode; 64*91f16700Schasinglulu struct dram_timing_info *timing_info; 65*91f16700Schasinglulu /* mr, emr, emr2, emr3, mr11, mr12, mr22, mr14 */ 66*91f16700Schasinglulu uint32_t mr_table[3][8]; 67*91f16700Schasinglulu /* used for workaround for rank to rank issue */ 68*91f16700Schasinglulu uint32_t rank_setting[3][3]; 69*91f16700Schasinglulu }; 70*91f16700Schasinglulu 71*91f16700Schasinglulu extern struct dram_info dram_info; 72*91f16700Schasinglulu 73*91f16700Schasinglulu void dram_info_init(unsigned long dram_timing_base); 74*91f16700Schasinglulu void dram_umctl2_init(struct dram_timing_info *timing); 75*91f16700Schasinglulu void dram_phy_init(struct dram_timing_info *timing); 76*91f16700Schasinglulu 77*91f16700Schasinglulu /* dram retention */ 78*91f16700Schasinglulu void dram_enter_retention(void); 79*91f16700Schasinglulu void dram_exit_retention(void); 80*91f16700Schasinglulu 81*91f16700Schasinglulu void dram_clock_switch(unsigned int target_drate, bool bypass_mode); 82*91f16700Schasinglulu 83*91f16700Schasinglulu /* dram frequency change */ 84*91f16700Schasinglulu void lpddr4_swffc(struct dram_info *info, unsigned int init_fsp, unsigned int fsp_index); 85*91f16700Schasinglulu void ddr4_swffc(struct dram_info *dram_info, unsigned int pstate); 86*91f16700Schasinglulu 87*91f16700Schasinglulu #endif /* DRAM_H */ 88