1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright 2019-2022 NXP 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #ifndef IMX_DDRC_H 8*91f16700Schasinglulu #define IMX_DDRC_H 9*91f16700Schasinglulu 10*91f16700Schasinglulu #define DDRC_IPS_BASE_ADDR(X) (0x3d400000 + ((X) * 0x2000000)) 11*91f16700Schasinglulu #define DDRC_DDR_SS_GPR0 0x3d000000 12*91f16700Schasinglulu 13*91f16700Schasinglulu /* DWC ddr umctl2 REGs offset*/ 14*91f16700Schasinglulu /**********************/ 15*91f16700Schasinglulu #define DDRC_MSTR(X) (DDRC_IPS_BASE_ADDR(X) + 0x00) 16*91f16700Schasinglulu #define DDRC_STAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x04) 17*91f16700Schasinglulu #define DDRC_MSTR1(X) (DDRC_IPS_BASE_ADDR(X) + 0x08) 18*91f16700Schasinglulu #define DDRC_MRCTRL0(X) (DDRC_IPS_BASE_ADDR(X) + 0x10) 19*91f16700Schasinglulu #define DDRC_MRCTRL1(X) (DDRC_IPS_BASE_ADDR(X) + 0x14) 20*91f16700Schasinglulu #define DDRC_MRSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x18) 21*91f16700Schasinglulu #define DDRC_MRCTRL2(X) (DDRC_IPS_BASE_ADDR(X) + 0x1c) 22*91f16700Schasinglulu #define DDRC_DERATEEN(X) (DDRC_IPS_BASE_ADDR(X) + 0x20) 23*91f16700Schasinglulu #define DDRC_DERATEINT(X) (DDRC_IPS_BASE_ADDR(X) + 0x24) 24*91f16700Schasinglulu #define DDRC_MSTR2(X) (DDRC_IPS_BASE_ADDR(X) + 0x28) 25*91f16700Schasinglulu #define DDRC_PWRCTL(X) (DDRC_IPS_BASE_ADDR(X) + 0x30) 26*91f16700Schasinglulu #define DDRC_PWRTMG(X) (DDRC_IPS_BASE_ADDR(X) + 0x34) 27*91f16700Schasinglulu #define DDRC_HWLPCTL(X) (DDRC_IPS_BASE_ADDR(X) + 0x38) 28*91f16700Schasinglulu #define DDRC_HWFFCCTL(X) (DDRC_IPS_BASE_ADDR(X) + 0x3c) 29*91f16700Schasinglulu #define DDRC_HWFFCSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x40) 30*91f16700Schasinglulu #define DDRC_RFSHCTL0(X) (DDRC_IPS_BASE_ADDR(X) + 0x50) 31*91f16700Schasinglulu #define DDRC_RFSHCTL1(X) (DDRC_IPS_BASE_ADDR(X) + 0x54) 32*91f16700Schasinglulu #define DDRC_RFSHCTL2(X) (DDRC_IPS_BASE_ADDR(X) + 0x58) 33*91f16700Schasinglulu #define DDRC_RFSHCTL3(X) (DDRC_IPS_BASE_ADDR(X) + 0x60) 34*91f16700Schasinglulu #define DDRC_RFSHTMG(X) (DDRC_IPS_BASE_ADDR(X) + 0x64) 35*91f16700Schasinglulu #define DDRC_ECCCFG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x70) 36*91f16700Schasinglulu #define DDRC_ECCCFG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x74) 37*91f16700Schasinglulu #define DDRC_ECCSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x78) 38*91f16700Schasinglulu #define DDRC_ECCCLR(X) (DDRC_IPS_BASE_ADDR(X) + 0x7c) 39*91f16700Schasinglulu #define DDRC_ECCERRCNT(X) (DDRC_IPS_BASE_ADDR(X) + 0x80) 40*91f16700Schasinglulu #define DDRC_ECCCADDR0(X) (DDRC_IPS_BASE_ADDR(X) + 0x84) 41*91f16700Schasinglulu #define DDRC_ECCCADDR1(X) (DDRC_IPS_BASE_ADDR(X) + 0x88) 42*91f16700Schasinglulu #define DDRC_ECCCSYN0(X) (DDRC_IPS_BASE_ADDR(X) + 0x8c) 43*91f16700Schasinglulu #define DDRC_ECCCSYN1(X) (DDRC_IPS_BASE_ADDR(X) + 0x90) 44*91f16700Schasinglulu #define DDRC_ECCCSYN2(X) (DDRC_IPS_BASE_ADDR(X) + 0x94) 45*91f16700Schasinglulu #define DDRC_ECCBITMASK0(X) (DDRC_IPS_BASE_ADDR(X) + 0x98) 46*91f16700Schasinglulu #define DDRC_ECCBITMASK1(X) (DDRC_IPS_BASE_ADDR(X) + 0x9c) 47*91f16700Schasinglulu #define DDRC_ECCBITMASK2(X) (DDRC_IPS_BASE_ADDR(X) + 0xa0) 48*91f16700Schasinglulu #define DDRC_ECCUADDR0(X) (DDRC_IPS_BASE_ADDR(X) + 0xa4) 49*91f16700Schasinglulu #define DDRC_ECCUADDR1(X) (DDRC_IPS_BASE_ADDR(X) + 0xa8) 50*91f16700Schasinglulu #define DDRC_ECCUSYN0(X) (DDRC_IPS_BASE_ADDR(X) + 0xac) 51*91f16700Schasinglulu #define DDRC_ECCUSYN1(X) (DDRC_IPS_BASE_ADDR(X) + 0xb0) 52*91f16700Schasinglulu #define DDRC_ECCUSYN2(X) (DDRC_IPS_BASE_ADDR(X) + 0xb4) 53*91f16700Schasinglulu #define DDRC_ECCPOISONADDR0(X) (DDRC_IPS_BASE_ADDR(X) + 0xb8) 54*91f16700Schasinglulu #define DDRC_ECCPOISONADDR1(X) (DDRC_IPS_BASE_ADDR(X) + 0xbc) 55*91f16700Schasinglulu #define DDRC_CRCPARCTL0(X) (DDRC_IPS_BASE_ADDR(X) + 0xc0) 56*91f16700Schasinglulu #define DDRC_CRCPARCTL1(X) (DDRC_IPS_BASE_ADDR(X) + 0xc4) 57*91f16700Schasinglulu #define DDRC_CRCPARCTL2(X) (DDRC_IPS_BASE_ADDR(X) + 0xc8) 58*91f16700Schasinglulu #define DDRC_CRCPARSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0xcc) 59*91f16700Schasinglulu #define DDRC_INIT0(X) (DDRC_IPS_BASE_ADDR(X) + 0xd0) 60*91f16700Schasinglulu #define DDRC_INIT1(X) (DDRC_IPS_BASE_ADDR(X) + 0xd4) 61*91f16700Schasinglulu #define DDRC_INIT2(X) (DDRC_IPS_BASE_ADDR(X) + 0xd8) 62*91f16700Schasinglulu #define DDRC_INIT3(X) (DDRC_IPS_BASE_ADDR(X) + 0xdc) 63*91f16700Schasinglulu #define DDRC_INIT4(X) (DDRC_IPS_BASE_ADDR(X) + 0xe0) 64*91f16700Schasinglulu #define DDRC_INIT5(X) (DDRC_IPS_BASE_ADDR(X) + 0xe4) 65*91f16700Schasinglulu #define DDRC_INIT6(X) (DDRC_IPS_BASE_ADDR(X) + 0xe8) 66*91f16700Schasinglulu #define DDRC_INIT7(X) (DDRC_IPS_BASE_ADDR(X) + 0xec) 67*91f16700Schasinglulu #define DDRC_DIMMCTL(X) (DDRC_IPS_BASE_ADDR(X) + 0xf0) 68*91f16700Schasinglulu #define DDRC_RANKCTL(X) (DDRC_IPS_BASE_ADDR(X) + 0xf4) 69*91f16700Schasinglulu #define DDRC_DRAMTMG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x100) 70*91f16700Schasinglulu #define DDRC_DRAMTMG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x104) 71*91f16700Schasinglulu #define DDRC_DRAMTMG2(X) (DDRC_IPS_BASE_ADDR(X) + 0x108) 72*91f16700Schasinglulu #define DDRC_DRAMTMG3(X) (DDRC_IPS_BASE_ADDR(X) + 0x10c) 73*91f16700Schasinglulu #define DDRC_DRAMTMG4(X) (DDRC_IPS_BASE_ADDR(X) + 0x110) 74*91f16700Schasinglulu #define DDRC_DRAMTMG5(X) (DDRC_IPS_BASE_ADDR(X) + 0x114) 75*91f16700Schasinglulu #define DDRC_DRAMTMG6(X) (DDRC_IPS_BASE_ADDR(X) + 0x118) 76*91f16700Schasinglulu #define DDRC_DRAMTMG7(X) (DDRC_IPS_BASE_ADDR(X) + 0x11c) 77*91f16700Schasinglulu #define DDRC_DRAMTMG8(X) (DDRC_IPS_BASE_ADDR(X) + 0x120) 78*91f16700Schasinglulu #define DDRC_DRAMTMG9(X) (DDRC_IPS_BASE_ADDR(X) + 0x124) 79*91f16700Schasinglulu #define DDRC_DRAMTMG10(X) (DDRC_IPS_BASE_ADDR(X) + 0x128) 80*91f16700Schasinglulu #define DDRC_DRAMTMG11(X) (DDRC_IPS_BASE_ADDR(X) + 0x12c) 81*91f16700Schasinglulu #define DDRC_DRAMTMG12(X) (DDRC_IPS_BASE_ADDR(X) + 0x130) 82*91f16700Schasinglulu #define DDRC_DRAMTMG13(X) (DDRC_IPS_BASE_ADDR(X) + 0x134) 83*91f16700Schasinglulu #define DDRC_DRAMTMG14(X) (DDRC_IPS_BASE_ADDR(X) + 0x138) 84*91f16700Schasinglulu #define DDRC_DRAMTMG15(X) (DDRC_IPS_BASE_ADDR(X) + 0x13C) 85*91f16700Schasinglulu #define DDRC_DRAMTMG16(X) (DDRC_IPS_BASE_ADDR(X) + 0x140) 86*91f16700Schasinglulu #define DDRC_DRAMTMG17(X) (DDRC_IPS_BASE_ADDR(X) + 0x144) 87*91f16700Schasinglulu 88*91f16700Schasinglulu #define DDRC_ZQCTL0(X) (DDRC_IPS_BASE_ADDR(X) + 0x180) 89*91f16700Schasinglulu #define DDRC_ZQCTL1(X) (DDRC_IPS_BASE_ADDR(X) + 0x184) 90*91f16700Schasinglulu #define DDRC_ZQCTL2(X) (DDRC_IPS_BASE_ADDR(X) + 0x188) 91*91f16700Schasinglulu #define DDRC_ZQSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x18c) 92*91f16700Schasinglulu #define DDRC_DFITMG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x190) 93*91f16700Schasinglulu #define DDRC_DFITMG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x194) 94*91f16700Schasinglulu #define DDRC_DFILPCFG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x198) 95*91f16700Schasinglulu #define DDRC_DFILPCFG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x19c) 96*91f16700Schasinglulu #define DDRC_DFIUPD0(X) (DDRC_IPS_BASE_ADDR(X) + 0x1a0) 97*91f16700Schasinglulu #define DDRC_DFIUPD1(X) (DDRC_IPS_BASE_ADDR(X) + 0x1a4) 98*91f16700Schasinglulu #define DDRC_DFIUPD2(X) (DDRC_IPS_BASE_ADDR(X) + 0x1a8) 99*91f16700Schasinglulu #define DDRC_DFIMISC(X) (DDRC_IPS_BASE_ADDR(X) + 0x1b0) 100*91f16700Schasinglulu #define DDRC_DFITMG2(X) (DDRC_IPS_BASE_ADDR(X) + 0x1b4) 101*91f16700Schasinglulu #define DDRC_DFITMG3(X) (DDRC_IPS_BASE_ADDR(X) + 0x1b8) 102*91f16700Schasinglulu #define DDRC_DFISTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x1bc) 103*91f16700Schasinglulu 104*91f16700Schasinglulu #define DDRC_DBICTL(X) (DDRC_IPS_BASE_ADDR(X) + 0x1c0) 105*91f16700Schasinglulu #define DDRC_DFIPHYMSTR(X) (DDRC_IPS_BASE_ADDR(X) + 0x1c4) 106*91f16700Schasinglulu #define DDRC_TRAINCTL0(X) (DDRC_IPS_BASE_ADDR(X) + 0x1d0) 107*91f16700Schasinglulu #define DDRC_TRAINCTL1(X) (DDRC_IPS_BASE_ADDR(X) + 0x1d4) 108*91f16700Schasinglulu #define DDRC_TRAINCTL2(X) (DDRC_IPS_BASE_ADDR(X) + 0x1d8) 109*91f16700Schasinglulu #define DDRC_TRAINSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x1dc) 110*91f16700Schasinglulu #define DDRC_ADDRMAP0(X) (DDRC_IPS_BASE_ADDR(X) + 0x200) 111*91f16700Schasinglulu #define DDRC_ADDRMAP1(X) (DDRC_IPS_BASE_ADDR(X) + 0x204) 112*91f16700Schasinglulu #define DDRC_ADDRMAP2(X) (DDRC_IPS_BASE_ADDR(X) + 0x208) 113*91f16700Schasinglulu #define DDRC_ADDRMAP3(X) (DDRC_IPS_BASE_ADDR(X) + 0x20c) 114*91f16700Schasinglulu #define DDRC_ADDRMAP4(X) (DDRC_IPS_BASE_ADDR(X) + 0x210) 115*91f16700Schasinglulu #define DDRC_ADDRMAP5(X) (DDRC_IPS_BASE_ADDR(X) + 0x214) 116*91f16700Schasinglulu #define DDRC_ADDRMAP6(X) (DDRC_IPS_BASE_ADDR(X) + 0x218) 117*91f16700Schasinglulu #define DDRC_ADDRMAP7(X) (DDRC_IPS_BASE_ADDR(X) + 0x21c) 118*91f16700Schasinglulu #define DDRC_ADDRMAP8(X) (DDRC_IPS_BASE_ADDR(X) + 0x220) 119*91f16700Schasinglulu #define DDRC_ADDRMAP9(X) (DDRC_IPS_BASE_ADDR(X) + 0x224) 120*91f16700Schasinglulu #define DDRC_ADDRMAP10(X) (DDRC_IPS_BASE_ADDR(X) + 0x228) 121*91f16700Schasinglulu #define DDRC_ADDRMAP11(X) (DDRC_IPS_BASE_ADDR(X) + 0x22c) 122*91f16700Schasinglulu 123*91f16700Schasinglulu #define DDRC_ODTCFG(X) (DDRC_IPS_BASE_ADDR(X) + 0x240) 124*91f16700Schasinglulu #define DDRC_ODTMAP(X) (DDRC_IPS_BASE_ADDR(X) + 0x244) 125*91f16700Schasinglulu #define DDRC_SCHED(X) (DDRC_IPS_BASE_ADDR(X) + 0x250) 126*91f16700Schasinglulu #define DDRC_SCHED1(X) (DDRC_IPS_BASE_ADDR(X) + 0x254) 127*91f16700Schasinglulu #define DDRC_PERFHPR1(X) (DDRC_IPS_BASE_ADDR(X) + 0x25c) 128*91f16700Schasinglulu #define DDRC_PERFLPR1(X) (DDRC_IPS_BASE_ADDR(X) + 0x264) 129*91f16700Schasinglulu #define DDRC_PERFWR1(X) (DDRC_IPS_BASE_ADDR(X) + 0x26c) 130*91f16700Schasinglulu #define DDRC_PERFVPR1(X) (DDRC_IPS_BASE_ADDR(X) + 0x274) 131*91f16700Schasinglulu 132*91f16700Schasinglulu #define DDRC_PERFVPW1(X) (DDRC_IPS_BASE_ADDR(X) + 0x278) 133*91f16700Schasinglulu 134*91f16700Schasinglulu #define DDRC_DQMAP0(X) (DDRC_IPS_BASE_ADDR(X) + 0x280) 135*91f16700Schasinglulu #define DDRC_DQMAP1(X) (DDRC_IPS_BASE_ADDR(X) + 0x284) 136*91f16700Schasinglulu #define DDRC_DQMAP2(X) (DDRC_IPS_BASE_ADDR(X) + 0x288) 137*91f16700Schasinglulu #define DDRC_DQMAP3(X) (DDRC_IPS_BASE_ADDR(X) + 0x28c) 138*91f16700Schasinglulu #define DDRC_DQMAP4(X) (DDRC_IPS_BASE_ADDR(X) + 0x290) 139*91f16700Schasinglulu #define DDRC_DQMAP5(X) (DDRC_IPS_BASE_ADDR(X) + 0x294) 140*91f16700Schasinglulu #define DDRC_DBG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x300) 141*91f16700Schasinglulu #define DDRC_DBG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x304) 142*91f16700Schasinglulu #define DDRC_DBGCAM(X) (DDRC_IPS_BASE_ADDR(X) + 0x308) 143*91f16700Schasinglulu #define DDRC_DBGCMD(X) (DDRC_IPS_BASE_ADDR(X) + 0x30c) 144*91f16700Schasinglulu #define DDRC_DBGSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x310) 145*91f16700Schasinglulu 146*91f16700Schasinglulu #define DDRC_SWCTL(X) (DDRC_IPS_BASE_ADDR(X) + 0x320) 147*91f16700Schasinglulu #define DDRC_SWSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x324) 148*91f16700Schasinglulu #define DDRC_OCPARCFG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x330) 149*91f16700Schasinglulu #define DDRC_OCPARCFG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x334) 150*91f16700Schasinglulu #define DDRC_OCPARCFG2(X) (DDRC_IPS_BASE_ADDR(X) + 0x338) 151*91f16700Schasinglulu #define DDRC_OCPARCFG3(X) (DDRC_IPS_BASE_ADDR(X) + 0x33c) 152*91f16700Schasinglulu #define DDRC_OCPARSTAT0(X) (DDRC_IPS_BASE_ADDR(X) + 0x340) 153*91f16700Schasinglulu #define DDRC_OCPARSTAT1(X) (DDRC_IPS_BASE_ADDR(X) + 0x344) 154*91f16700Schasinglulu #define DDRC_OCPARWLOG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x348) 155*91f16700Schasinglulu #define DDRC_OCPARWLOG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x34c) 156*91f16700Schasinglulu #define DDRC_OCPARWLOG2(X) (DDRC_IPS_BASE_ADDR(X) + 0x350) 157*91f16700Schasinglulu #define DDRC_OCPARAWLOG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x354) 158*91f16700Schasinglulu #define DDRC_OCPARAWLOG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x358) 159*91f16700Schasinglulu #define DDRC_OCPARRLOG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x35c) 160*91f16700Schasinglulu #define DDRC_OCPARRLOG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x360) 161*91f16700Schasinglulu #define DDRC_OCPARARLOG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x364) 162*91f16700Schasinglulu #define DDRC_OCPARARLOG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x368) 163*91f16700Schasinglulu #define DDRC_POISONCFG(X) (DDRC_IPS_BASE_ADDR(X) + 0x36C) 164*91f16700Schasinglulu #define DDRC_POISONSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x370) 165*91f16700Schasinglulu #define DDRC_ADVECCINDEX(X) (DDRC_IPS_BASE_ADDR(X) + 0x3) 166*91f16700Schasinglulu #define DDRC_ADVECCSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x3) 167*91f16700Schasinglulu #define DDRC_ECCPOISONPAT0(X) (DDRC_IPS_BASE_ADDR(X) + 0x3) 168*91f16700Schasinglulu #define DDRC_ECCPOISONPAT1(X) (DDRC_IPS_BASE_ADDR(X) + 0x3) 169*91f16700Schasinglulu #define DDRC_ECCPOISONPAT2(X) (DDRC_IPS_BASE_ADDR(X) + 0x3) 170*91f16700Schasinglulu #define DDRC_HIFCTL(X) (DDRC_IPS_BASE_ADDR(X) + 0x3) 171*91f16700Schasinglulu 172*91f16700Schasinglulu #define DDRC_PSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x3fc) 173*91f16700Schasinglulu #define DDRC_PCCFG(X) (DDRC_IPS_BASE_ADDR(X) + 0x400) 174*91f16700Schasinglulu #define DDRC_PCFGR_0(X) (DDRC_IPS_BASE_ADDR(X) + 0x404) 175*91f16700Schasinglulu #define DDRC_PCFGR_1(X) (DDRC_IPS_BASE_ADDR(X) + 1 * 0xb0 + 0x404) 176*91f16700Schasinglulu #define DDRC_PCFGR_2(X) (DDRC_IPS_BASE_ADDR(X) + 2 * 0xb0 + 0x404) 177*91f16700Schasinglulu #define DDRC_PCFGR_3(X) (DDRC_IPS_BASE_ADDR(X) + 3 * 0xb0 + 0x404) 178*91f16700Schasinglulu #define DDRC_PCFGW_0(X) (DDRC_IPS_BASE_ADDR(X) + 0x408) 179*91f16700Schasinglulu #define DDRC_PCFGW_1(X) (DDRC_IPS_BASE_ADDR(X) + 1 * 0xb0 + 0x408) 180*91f16700Schasinglulu #define DDRC_PCFGW_2(X) (DDRC_IPS_BASE_ADDR(X) + 2 * 0xb0 + 0x408) 181*91f16700Schasinglulu #define DDRC_PCFGW_3(X) (DDRC_IPS_BASE_ADDR(X) + 3 * 0xb0 + 0x408) 182*91f16700Schasinglulu #define DDRC_PCFGC_0(X) (DDRC_IPS_BASE_ADDR(X) + 0x40c) 183*91f16700Schasinglulu #define DDRC_PCFGIDMASKCH(X) (DDRC_IPS_BASE_ADDR(X) + 0x410) 184*91f16700Schasinglulu #define DDRC_PCFGIDVALUECH(X) (DDRC_IPS_BASE_ADDR(X) + 0x414) 185*91f16700Schasinglulu #define DDRC_PCTRL_0(X) (DDRC_IPS_BASE_ADDR(X) + 0x490) 186*91f16700Schasinglulu #define DDRC_PCTRL_1(X) (DDRC_IPS_BASE_ADDR(X) + 0x490 + 1 * 0xb0) 187*91f16700Schasinglulu #define DDRC_PCTRL_2(X) (DDRC_IPS_BASE_ADDR(X) + 0x490 + 2 * 0xb0) 188*91f16700Schasinglulu #define DDRC_PCTRL_3(X) (DDRC_IPS_BASE_ADDR(X) + 0x490 + 3 * 0xb0) 189*91f16700Schasinglulu #define DDRC_PCFGQOS0_0(X) (DDRC_IPS_BASE_ADDR(X) + 0x494) 190*91f16700Schasinglulu #define DDRC_PCFGQOS1_0(X) (DDRC_IPS_BASE_ADDR(X) + 0x498) 191*91f16700Schasinglulu #define DDRC_PCFGWQOS0_0(X) (DDRC_IPS_BASE_ADDR(X) + 0x49c) 192*91f16700Schasinglulu #define DDRC_PCFGWQOS1_0(X) (DDRC_IPS_BASE_ADDR(X) + 0x4a0) 193*91f16700Schasinglulu #define DDRC_SARBASE0(X) (DDRC_IPS_BASE_ADDR(X) + 0xf04) 194*91f16700Schasinglulu #define DDRC_SARSIZE0(X) (DDRC_IPS_BASE_ADDR(X) + 0xf08) 195*91f16700Schasinglulu #define DDRC_SBRCTL(X) (DDRC_IPS_BASE_ADDR(X) + 0xf24) 196*91f16700Schasinglulu #define DDRC_SBRSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0xf28) 197*91f16700Schasinglulu #define DDRC_SBRWDATA0(X) (DDRC_IPS_BASE_ADDR(X) + 0xf2c) 198*91f16700Schasinglulu #define DDRC_SBRWDATA1(X) (DDRC_IPS_BASE_ADDR(X) + 0xf30) 199*91f16700Schasinglulu #define DDRC_PDCH(X) (DDRC_IPS_BASE_ADDR(X) + 0xf34) 200*91f16700Schasinglulu 201*91f16700Schasinglulu /* SHADOW registers */ 202*91f16700Schasinglulu #define DDRC_FREQ1_DERATEEN(X) (DDRC_IPS_BASE_ADDR(X) + 0x2020) 203*91f16700Schasinglulu #define DDRC_FREQ1_DERATEINT(X) (DDRC_IPS_BASE_ADDR(X) + 0x2024) 204*91f16700Schasinglulu #define DDRC_FREQ1_RFSHCTL0(X) (DDRC_IPS_BASE_ADDR(X) + 0x2050) 205*91f16700Schasinglulu #define DDRC_FREQ1_RFSHTMG(X) (DDRC_IPS_BASE_ADDR(X) + 0x2064) 206*91f16700Schasinglulu #define DDRC_FREQ1_INIT3(X) (DDRC_IPS_BASE_ADDR(X) + 0x20dc) 207*91f16700Schasinglulu #define DDRC_FREQ1_INIT4(X) (DDRC_IPS_BASE_ADDR(X) + 0x20e0) 208*91f16700Schasinglulu #define DDRC_FREQ1_INIT6(X) (DDRC_IPS_BASE_ADDR(X) + 0x20e8) 209*91f16700Schasinglulu #define DDRC_FREQ1_INIT7(X) (DDRC_IPS_BASE_ADDR(X) + 0x20ec) 210*91f16700Schasinglulu #define DDRC_FREQ1_DRAMTMG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x2100) 211*91f16700Schasinglulu #define DDRC_FREQ1_DRAMTMG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x2104) 212*91f16700Schasinglulu #define DDRC_FREQ1_DRAMTMG2(X) (DDRC_IPS_BASE_ADDR(X) + 0x2108) 213*91f16700Schasinglulu #define DDRC_FREQ1_DRAMTMG3(X) (DDRC_IPS_BASE_ADDR(X) + 0x210c) 214*91f16700Schasinglulu #define DDRC_FREQ1_DRAMTMG4(X) (DDRC_IPS_BASE_ADDR(X) + 0x2110) 215*91f16700Schasinglulu #define DDRC_FREQ1_DRAMTMG5(X) (DDRC_IPS_BASE_ADDR(X) + 0x2114) 216*91f16700Schasinglulu #define DDRC_FREQ1_DRAMTMG6(X) (DDRC_IPS_BASE_ADDR(X) + 0x2118) 217*91f16700Schasinglulu #define DDRC_FREQ1_DRAMTMG7(X) (DDRC_IPS_BASE_ADDR(X) + 0x211c) 218*91f16700Schasinglulu #define DDRC_FREQ1_DRAMTMG8(X) (DDRC_IPS_BASE_ADDR(X) + 0x2120) 219*91f16700Schasinglulu #define DDRC_FREQ1_DRAMTMG9(X) (DDRC_IPS_BASE_ADDR(X) + 0x2124) 220*91f16700Schasinglulu #define DDRC_FREQ1_DRAMTMG10(X) (DDRC_IPS_BASE_ADDR(X) + 0x2128) 221*91f16700Schasinglulu #define DDRC_FREQ1_DRAMTMG11(X) (DDRC_IPS_BASE_ADDR(X) + 0x212c) 222*91f16700Schasinglulu #define DDRC_FREQ1_DRAMTMG12(X) (DDRC_IPS_BASE_ADDR(X) + 0x2130) 223*91f16700Schasinglulu #define DDRC_FREQ1_DRAMTMG13(X) (DDRC_IPS_BASE_ADDR(X) + 0x2134) 224*91f16700Schasinglulu #define DDRC_FREQ1_DRAMTMG14(X) (DDRC_IPS_BASE_ADDR(X) + 0x2138) 225*91f16700Schasinglulu #define DDRC_FREQ1_DRAMTMG15(X) (DDRC_IPS_BASE_ADDR(X) + 0x213C) 226*91f16700Schasinglulu #define DDRC_FREQ1_DRAMTMG16(X) (DDRC_IPS_BASE_ADDR(X) + 0x2140) 227*91f16700Schasinglulu #define DDRC_FREQ1_DRAMTMG17(X) (DDRC_IPS_BASE_ADDR(X) + 0x2144) 228*91f16700Schasinglulu #define DDRC_FREQ1_ZQCTL0(X) (DDRC_IPS_BASE_ADDR(X) + 0x2180) 229*91f16700Schasinglulu #define DDRC_FREQ1_DFITMG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x2190) 230*91f16700Schasinglulu #define DDRC_FREQ1_DFITMG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x2194) 231*91f16700Schasinglulu #define DDRC_FREQ1_DFITMG2(X) (DDRC_IPS_BASE_ADDR(X) + 0x21b4) 232*91f16700Schasinglulu #define DDRC_FREQ1_DFITMG3(X) (DDRC_IPS_BASE_ADDR(X) + 0x21b8) 233*91f16700Schasinglulu #define DDRC_FREQ1_ODTCFG(X) (DDRC_IPS_BASE_ADDR(X) + 0x2240) 234*91f16700Schasinglulu 235*91f16700Schasinglulu #define DDRC_FREQ2_DERATEEN(X) (DDRC_IPS_BASE_ADDR(X) + 0x3020) 236*91f16700Schasinglulu #define DDRC_FREQ2_DERATEINT(X) (DDRC_IPS_BASE_ADDR(X) + 0x3024) 237*91f16700Schasinglulu #define DDRC_FREQ2_RFSHCTL0(X) (DDRC_IPS_BASE_ADDR(X) + 0x3050) 238*91f16700Schasinglulu #define DDRC_FREQ2_RFSHTMG(X) (DDRC_IPS_BASE_ADDR(X) + 0x3064) 239*91f16700Schasinglulu #define DDRC_FREQ2_INIT3(X) (DDRC_IPS_BASE_ADDR(X) + 0x30dc) 240*91f16700Schasinglulu #define DDRC_FREQ2_INIT4(X) (DDRC_IPS_BASE_ADDR(X) + 0x30e0) 241*91f16700Schasinglulu #define DDRC_FREQ2_INIT6(X) (DDRC_IPS_BASE_ADDR(X) + 0x30e8) 242*91f16700Schasinglulu #define DDRC_FREQ2_INIT7(X) (DDRC_IPS_BASE_ADDR(X) + 0x30ec) 243*91f16700Schasinglulu #define DDRC_FREQ2_DRAMTMG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x3100) 244*91f16700Schasinglulu #define DDRC_FREQ2_DRAMTMG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x3104) 245*91f16700Schasinglulu #define DDRC_FREQ2_DRAMTMG2(X) (DDRC_IPS_BASE_ADDR(X) + 0x3108) 246*91f16700Schasinglulu #define DDRC_FREQ2_DRAMTMG3(X) (DDRC_IPS_BASE_ADDR(X) + 0x310c) 247*91f16700Schasinglulu #define DDRC_FREQ2_DRAMTMG4(X) (DDRC_IPS_BASE_ADDR(X) + 0x3110) 248*91f16700Schasinglulu #define DDRC_FREQ2_DRAMTMG5(X) (DDRC_IPS_BASE_ADDR(X) + 0x3114) 249*91f16700Schasinglulu #define DDRC_FREQ2_DRAMTMG6(X) (DDRC_IPS_BASE_ADDR(X) + 0x3118) 250*91f16700Schasinglulu #define DDRC_FREQ2_DRAMTMG7(X) (DDRC_IPS_BASE_ADDR(X) + 0x311c) 251*91f16700Schasinglulu #define DDRC_FREQ2_DRAMTMG8(X) (DDRC_IPS_BASE_ADDR(X) + 0x3120) 252*91f16700Schasinglulu #define DDRC_FREQ2_DRAMTMG9(X) (DDRC_IPS_BASE_ADDR(X) + 0x3124) 253*91f16700Schasinglulu #define DDRC_FREQ2_DRAMTMG10(X) (DDRC_IPS_BASE_ADDR(X) + 0x3128) 254*91f16700Schasinglulu #define DDRC_FREQ2_DRAMTMG11(X) (DDRC_IPS_BASE_ADDR(X) + 0x312c) 255*91f16700Schasinglulu #define DDRC_FREQ2_DRAMTMG12(X) (DDRC_IPS_BASE_ADDR(X) + 0x3130) 256*91f16700Schasinglulu #define DDRC_FREQ2_DRAMTMG13(X) (DDRC_IPS_BASE_ADDR(X) + 0x3134) 257*91f16700Schasinglulu #define DDRC_FREQ2_DRAMTMG14(X) (DDRC_IPS_BASE_ADDR(X) + 0x3138) 258*91f16700Schasinglulu #define DDRC_FREQ2_DRAMTMG15(X) (DDRC_IPS_BASE_ADDR(X) + 0x313C) 259*91f16700Schasinglulu #define DDRC_FREQ2_DRAMTMG16(X) (DDRC_IPS_BASE_ADDR(X) + 0x3140) 260*91f16700Schasinglulu #define DDRC_FREQ2_DRAMTMG17(X) (DDRC_IPS_BASE_ADDR(X) + 0x3144) 261*91f16700Schasinglulu #define DDRC_FREQ2_ZQCTL0(X) (DDRC_IPS_BASE_ADDR(X) + 0x3180) 262*91f16700Schasinglulu #define DDRC_FREQ2_DFITMG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x3190) 263*91f16700Schasinglulu #define DDRC_FREQ2_DFITMG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x3194) 264*91f16700Schasinglulu #define DDRC_FREQ2_DFITMG2(X) (DDRC_IPS_BASE_ADDR(X) + 0x31b4) 265*91f16700Schasinglulu #define DDRC_FREQ2_DFITMG3(X) (DDRC_IPS_BASE_ADDR(X) + 0x31b8) 266*91f16700Schasinglulu #define DDRC_FREQ2_ODTCFG(X) (DDRC_IPS_BASE_ADDR(X) + 0x3240) 267*91f16700Schasinglulu 268*91f16700Schasinglulu #define DDRC_FREQ3_DERATEEN(X) (DDRC_IPS_BASE_ADDR(X) + 0x4020) 269*91f16700Schasinglulu #define DDRC_FREQ3_DERATEINT(X) (DDRC_IPS_BASE_ADDR(X) + 0x4024) 270*91f16700Schasinglulu #define DDRC_FREQ3_RFSHCTL0(X) (DDRC_IPS_BASE_ADDR(X) + 0x4050) 271*91f16700Schasinglulu #define DDRC_FREQ3_RFSHTMG(X) (DDRC_IPS_BASE_ADDR(X) + 0x4064) 272*91f16700Schasinglulu #define DDRC_FREQ3_INIT3(X) (DDRC_IPS_BASE_ADDR(X) + 0x40dc) 273*91f16700Schasinglulu #define DDRC_FREQ3_INIT4(X) (DDRC_IPS_BASE_ADDR(X) + 0x40e0) 274*91f16700Schasinglulu #define DDRC_FREQ3_INIT6(X) (DDRC_IPS_BASE_ADDR(X) + 0x40e8) 275*91f16700Schasinglulu #define DDRC_FREQ3_INIT7(X) (DDRC_IPS_BASE_ADDR(X) + 0x40ec) 276*91f16700Schasinglulu #define DDRC_FREQ3_DRAMTMG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x4100) 277*91f16700Schasinglulu #define DDRC_FREQ3_DRAMTMG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x4104) 278*91f16700Schasinglulu #define DDRC_FREQ3_DRAMTMG2(X) (DDRC_IPS_BASE_ADDR(X) + 0x4108) 279*91f16700Schasinglulu #define DDRC_FREQ3_DRAMTMG3(X) (DDRC_IPS_BASE_ADDR(X) + 0x410c) 280*91f16700Schasinglulu #define DDRC_FREQ3_DRAMTMG4(X) (DDRC_IPS_BASE_ADDR(X) + 0x4110) 281*91f16700Schasinglulu #define DDRC_FREQ3_DRAMTMG5(X) (DDRC_IPS_BASE_ADDR(X) + 0x4114) 282*91f16700Schasinglulu #define DDRC_FREQ3_DRAMTMG6(X) (DDRC_IPS_BASE_ADDR(X) + 0x4118) 283*91f16700Schasinglulu #define DDRC_FREQ3_DRAMTMG7(X) (DDRC_IPS_BASE_ADDR(X) + 0x411c) 284*91f16700Schasinglulu #define DDRC_FREQ3_DRAMTMG8(X) (DDRC_IPS_BASE_ADDR(X) + 0x4120) 285*91f16700Schasinglulu #define DDRC_FREQ3_DRAMTMG9(X) (DDRC_IPS_BASE_ADDR(X) + 0x4124) 286*91f16700Schasinglulu #define DDRC_FREQ3_DRAMTMG10(X) (DDRC_IPS_BASE_ADDR(X) + 0x4128) 287*91f16700Schasinglulu #define DDRC_FREQ3_DRAMTMG11(X) (DDRC_IPS_BASE_ADDR(X) + 0x412c) 288*91f16700Schasinglulu #define DDRC_FREQ3_DRAMTMG12(X) (DDRC_IPS_BASE_ADDR(X) + 0x4130) 289*91f16700Schasinglulu #define DDRC_FREQ3_DRAMTMG13(X) (DDRC_IPS_BASE_ADDR(X) + 0x4134) 290*91f16700Schasinglulu #define DDRC_FREQ3_DRAMTMG14(X) (DDRC_IPS_BASE_ADDR(X) + 0x4138) 291*91f16700Schasinglulu #define DDRC_FREQ3_DRAMTMG15(X) (DDRC_IPS_BASE_ADDR(X) + 0x413C) 292*91f16700Schasinglulu #define DDRC_FREQ3_DRAMTMG16(X) (DDRC_IPS_BASE_ADDR(X) + 0x4140) 293*91f16700Schasinglulu 294*91f16700Schasinglulu #define DDRC_FREQ3_ZQCTL0(X) (DDRC_IPS_BASE_ADDR(X) + 0x4180) 295*91f16700Schasinglulu #define DDRC_FREQ3_DFITMG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x4190) 296*91f16700Schasinglulu #define DDRC_FREQ3_DFITMG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x4194) 297*91f16700Schasinglulu #define DDRC_FREQ3_DFITMG2(X) (DDRC_IPS_BASE_ADDR(X) + 0x41b4) 298*91f16700Schasinglulu #define DDRC_FREQ3_DFITMG3(X) (DDRC_IPS_BASE_ADDR(X) + 0x41b8) 299*91f16700Schasinglulu #define DDRC_FREQ3_ODTCFG(X) (DDRC_IPS_BASE_ADDR(X) + 0x4240) 300*91f16700Schasinglulu #define DDRC_DFITMG0_SHADOW(X) (DDRC_IPS_BASE_ADDR(X) + 0x2190) 301*91f16700Schasinglulu #define DDRC_DFITMG1_SHADOW(X) (DDRC_IPS_BASE_ADDR(X) + 0x2194) 302*91f16700Schasinglulu #define DDRC_DFITMG2_SHADOW(X) (DDRC_IPS_BASE_ADDR(X) + 0x21b4) 303*91f16700Schasinglulu #define DDRC_DFITMG3_SHADOW(X) (DDRC_IPS_BASE_ADDR(X) + 0x21b8) 304*91f16700Schasinglulu #define DDRC_ODTCFG_SHADOW(X) (DDRC_IPS_BASE_ADDR(X) + 0x2240) 305*91f16700Schasinglulu 306*91f16700Schasinglulu #define DRC_PERF_MON_BASE_ADDR(X) (0x3d800000 + ((X) * 0x2000000)) 307*91f16700Schasinglulu #define DRC_PERF_MON_CNT0_CTL(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x0) 308*91f16700Schasinglulu #define DRC_PERF_MON_CNT1_CTL(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x4) 309*91f16700Schasinglulu #define DRC_PERF_MON_CNT2_CTL(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x8) 310*91f16700Schasinglulu #define DRC_PERF_MON_CNT3_CTL(X) (DRC_PERF_MON_BASE_ADDR(X) + 0xC) 311*91f16700Schasinglulu #define DRC_PERF_MON_CNT0_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x20) 312*91f16700Schasinglulu #define DRC_PERF_MON_CNT1_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x24) 313*91f16700Schasinglulu #define DRC_PERF_MON_CNT2_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x28) 314*91f16700Schasinglulu #define DRC_PERF_MON_CNT3_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x2C) 315*91f16700Schasinglulu #define DRC_PERF_MON_DPCR_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x30) 316*91f16700Schasinglulu #define DRC_PERF_MON_MRR0_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x40) 317*91f16700Schasinglulu #define DRC_PERF_MON_MRR1_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x44) 318*91f16700Schasinglulu #define DRC_PERF_MON_MRR2_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x48) 319*91f16700Schasinglulu #define DRC_PERF_MON_MRR3_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x4C) 320*91f16700Schasinglulu #define DRC_PERF_MON_MRR4_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x50) 321*91f16700Schasinglulu #define DRC_PERF_MON_MRR5_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x54) 322*91f16700Schasinglulu #define DRC_PERF_MON_MRR6_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x58) 323*91f16700Schasinglulu #define DRC_PERF_MON_MRR7_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x5C) 324*91f16700Schasinglulu #define DRC_PERF_MON_MRR8_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x60) 325*91f16700Schasinglulu #define DRC_PERF_MON_MRR9_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x64) 326*91f16700Schasinglulu #define DRC_PERF_MON_MRR10_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x68) 327*91f16700Schasinglulu #define DRC_PERF_MON_MRR11_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x6C) 328*91f16700Schasinglulu #define DRC_PERF_MON_MRR12_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x70) 329*91f16700Schasinglulu #define DRC_PERF_MON_MRR13_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x74) 330*91f16700Schasinglulu #define DRC_PERF_MON_MRR14_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x78) 331*91f16700Schasinglulu #define DRC_PERF_MON_MRR15_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x7C) 332*91f16700Schasinglulu 333*91f16700Schasinglulu #define dwc_ddrphy_apb_rd(addr) mmio_read_32(IMX_DDRPHY_BASE + 4 * (addr)) 334*91f16700Schasinglulu #define dwc_ddrphy_apb_wr(addr, val) mmio_write_32(IMX_DDRPHY_BASE + 4 * (addr), val) 335*91f16700Schasinglulu 336*91f16700Schasinglulu #endif /*IMX_DDRC_H */ 337