1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #include <stdint.h> 8*91f16700Schasinglulu 9*91f16700Schasinglulu #define MU_ATR0_OFFSET1 0x0 10*91f16700Schasinglulu #define MU_ARR0_OFFSET1 0x10 11*91f16700Schasinglulu #define MU_ASR_OFFSET1 0x20 12*91f16700Schasinglulu #define MU_ACR_OFFSET1 0x24 13*91f16700Schasinglulu #define MU_TR_COUNT1 4 14*91f16700Schasinglulu #define MU_RR_COUNT1 4 15*91f16700Schasinglulu 16*91f16700Schasinglulu #define MU_CR_GIEn_MASK1 (0xFu << 28) 17*91f16700Schasinglulu #define MU_CR_RIEn_MASK1 (0xF << 24) 18*91f16700Schasinglulu #define MU_CR_TIEn_MASK1 (0xF << 20) 19*91f16700Schasinglulu #define MU_CR_GIRn_MASK1 (0xF << 16) 20*91f16700Schasinglulu #define MU_CR_NMI_MASK1 (1 << 3) 21*91f16700Schasinglulu #define MU_CR_Fn_MASK1 0x7 22*91f16700Schasinglulu 23*91f16700Schasinglulu #define MU_SR_TE0_MASK1 (1 << 23) 24*91f16700Schasinglulu #define MU_SR_RF0_MASK1 (1 << 27) 25*91f16700Schasinglulu #define MU_CR_RIE0_MASK1 (1 << 27) 26*91f16700Schasinglulu #define MU_CR_GIE0_MASK1 (1U << 31) 27*91f16700Schasinglulu 28*91f16700Schasinglulu #define MU_TR_COUNT 4 29*91f16700Schasinglulu #define MU_RR_COUNT 4 30*91f16700Schasinglulu 31*91f16700Schasinglulu void MU_Init(uint32_t base); 32*91f16700Schasinglulu void MU_SendMessage(uint32_t base, uint32_t regIndex, uint32_t msg); 33*91f16700Schasinglulu void MU_ReceiveMsg(uint32_t base, uint32_t regIndex, uint32_t *msg); 34*91f16700Schasinglulu void MU_EnableGeneralInt(uint32_t base, uint32_t index); 35*91f16700Schasinglulu void MU_EnableRxFullInt(uint32_t base, uint32_t index); 36*91f16700Schasinglulu void MU_Resume(uint32_t base); 37