1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (C) 2018-2019, ARM Limited and Contributors. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu #ifndef IMX_SNVS_H 7*91f16700Schasinglulu #define IMX_SNVS_H 8*91f16700Schasinglulu 9*91f16700Schasinglulu #include <cdefs.h> 10*91f16700Schasinglulu #include <stdint.h> 11*91f16700Schasinglulu 12*91f16700Schasinglulu #include <arch.h> 13*91f16700Schasinglulu 14*91f16700Schasinglulu struct snvs { 15*91f16700Schasinglulu uint32_t hplr; 16*91f16700Schasinglulu uint32_t hpcomr; 17*91f16700Schasinglulu uint32_t hpcr; 18*91f16700Schasinglulu uint32_t hpsicr; 19*91f16700Schasinglulu uint32_t hpsvcr; 20*91f16700Schasinglulu uint32_t hpsr; 21*91f16700Schasinglulu uint32_t hpsvsr; 22*91f16700Schasinglulu uint32_t hphacivr; 23*91f16700Schasinglulu uint32_t hphacr; 24*91f16700Schasinglulu uint32_t hprtcmr; 25*91f16700Schasinglulu uint32_t hprtclr; 26*91f16700Schasinglulu uint32_t hptamr; 27*91f16700Schasinglulu uint32_t hptalr; 28*91f16700Schasinglulu uint32_t lplr; 29*91f16700Schasinglulu uint32_t lpcr; 30*91f16700Schasinglulu uint32_t lpmkcr; 31*91f16700Schasinglulu uint32_t lpsvcr; 32*91f16700Schasinglulu uint32_t lptgfcr; 33*91f16700Schasinglulu uint32_t lptdcr; 34*91f16700Schasinglulu uint32_t lpsr; 35*91f16700Schasinglulu uint32_t lpsrtcmr; 36*91f16700Schasinglulu uint32_t lpsrtclr; 37*91f16700Schasinglulu uint32_t lptar; 38*91f16700Schasinglulu uint32_t lpsmcmr; 39*91f16700Schasinglulu uint32_t lpsmclr; 40*91f16700Schasinglulu uint32_t lppgdr; 41*91f16700Schasinglulu uint32_t lpgpr0_alias; 42*91f16700Schasinglulu uint8_t lpzmkr[32]; 43*91f16700Schasinglulu uint16_t res0; 44*91f16700Schasinglulu uint32_t lpgpr0[4]; 45*91f16700Schasinglulu uint32_t lptdc2r; 46*91f16700Schasinglulu uint32_t lptdsr; 47*91f16700Schasinglulu uint32_t lptgf1cr; 48*91f16700Schasinglulu uint32_t lptgf2cr; 49*91f16700Schasinglulu uint32_t res1[4]; 50*91f16700Schasinglulu uint32_t lpat1cr; 51*91f16700Schasinglulu uint32_t lpat2cr; 52*91f16700Schasinglulu uint32_t lpat3cr; 53*91f16700Schasinglulu uint32_t lpat4cr; 54*91f16700Schasinglulu uint32_t lpat5cr; 55*91f16700Schasinglulu uint32_t res2[3]; 56*91f16700Schasinglulu uint32_t lpatctlr; 57*91f16700Schasinglulu uint32_t lpatclkr; 58*91f16700Schasinglulu uint32_t lpatrc1r; 59*91f16700Schasinglulu uint32_t lpatrc2r; 60*91f16700Schasinglulu uint32_t res3[706]; 61*91f16700Schasinglulu uint32_t hpvidr1; 62*91f16700Schasinglulu uint32_t hpvidr2; 63*91f16700Schasinglulu } __packed; 64*91f16700Schasinglulu 65*91f16700Schasinglulu /* Define the HPCOMR bits */ 66*91f16700Schasinglulu #define HPCOMR_NPSWA_EN BIT(31) 67*91f16700Schasinglulu #define HPCOMR_HAC_STOP BIT(19) 68*91f16700Schasinglulu #define HPCOMR_HAC_CLEAR BIT(18) 69*91f16700Schasinglulu #define HPCOMR_HAC_LOAD BIT(17) 70*91f16700Schasinglulu #define HPCOMR_HAC_EN BIT(16) 71*91f16700Schasinglulu #define HPCOMR_MKS_EN BIT(13) 72*91f16700Schasinglulu #define HPCOMR_PROG_ZMK BIT(12) 73*91f16700Schasinglulu #define HPCOMR_SW_LPSV BIT(10) 74*91f16700Schasinglulu #define HPCOMR_SW_FSV BIT(9) 75*91f16700Schasinglulu #define HPCOMR_SW_SV BIT(8) 76*91f16700Schasinglulu #define HPCOMR_LP_SWR_DIS BIT(5) 77*91f16700Schasinglulu #define HPCOMR_LP_SWR BIT(4) 78*91f16700Schasinglulu #define HPCOMR_SSM_SFNS_DIS BIT(2) 79*91f16700Schasinglulu #define HPCOMR_SSM_ST_DIS BIT(1) 80*91f16700Schasinglulu #define HPCOMR_SSM_ST BIT(0) 81*91f16700Schasinglulu 82*91f16700Schasinglulu void imx_snvs_init(void); 83*91f16700Schasinglulu 84*91f16700Schasinglulu #endif /* IMX_SNVS_H */ 85