1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2015-2023, ARM Limited and Contributors. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #ifndef __IMX_SIP_SVC_H__ 8*91f16700Schasinglulu #define __IMX_SIP_SVC_H__ 9*91f16700Schasinglulu 10*91f16700Schasinglulu /* SMC function IDs for SiP Service queries */ 11*91f16700Schasinglulu #define IMX_SIP_GPC 0xC2000000 12*91f16700Schasinglulu 13*91f16700Schasinglulu #define IMX_SIP_CPUFREQ 0xC2000001 14*91f16700Schasinglulu #define IMX_SIP_SET_CPUFREQ 0x00 15*91f16700Schasinglulu 16*91f16700Schasinglulu #define IMX_SIP_SRTC 0xC2000002 17*91f16700Schasinglulu #define IMX_SIP_SRTC_SET_TIME 0x00 18*91f16700Schasinglulu 19*91f16700Schasinglulu #define IMX_SIP_BUILDINFO 0xC2000003 20*91f16700Schasinglulu #define IMX_SIP_BUILDINFO_GET_COMMITHASH 0x00 21*91f16700Schasinglulu 22*91f16700Schasinglulu #define IMX_SIP_DDR_DVFS 0xc2000004 23*91f16700Schasinglulu 24*91f16700Schasinglulu #define IMX_SIP_SRC 0xC2000005 25*91f16700Schasinglulu #define IMX_SIP_SRC_SET_SECONDARY_BOOT 0x10 26*91f16700Schasinglulu #define IMX_SIP_SRC_IS_SECONDARY_BOOT 0x11 27*91f16700Schasinglulu 28*91f16700Schasinglulu #define IMX_SIP_GET_SOC_INFO 0xC2000006 29*91f16700Schasinglulu 30*91f16700Schasinglulu #define IMX_SIP_HAB 0xC2000007 31*91f16700Schasinglulu #define IMX_SIP_HAB_AUTH_IMG 0x00 32*91f16700Schasinglulu #define IMX_SIP_HAB_ENTRY 0x01 33*91f16700Schasinglulu #define IMX_SIP_HAB_EXIT 0x02 34*91f16700Schasinglulu #define IMX_SIP_HAB_REPORT_EVENT 0x03 35*91f16700Schasinglulu #define IMX_SIP_HAB_REPORT_STATUS 0x04 36*91f16700Schasinglulu #define IMX_SIP_HAB_FAILSAFE 0x05 37*91f16700Schasinglulu #define IMX_SIP_HAB_CHECK_TARGET 0x06 38*91f16700Schasinglulu #define IMX_SIP_HAB_GET_VERSION 0x07 39*91f16700Schasinglulu #define IMX_SIP_HAB_AUTH_IMG_NO_DCD 0x08 40*91f16700Schasinglulu 41*91f16700Schasinglulu #define IMX_SIP_WAKEUP_SRC 0xC2000009 42*91f16700Schasinglulu #define IMX_SIP_WAKEUP_SRC_SCU 0x1 43*91f16700Schasinglulu #define IMX_SIP_WAKEUP_SRC_IRQSTEER 0x2 44*91f16700Schasinglulu 45*91f16700Schasinglulu #define IMX_SIP_OTP_READ 0xC200000A 46*91f16700Schasinglulu #define IMX_SIP_OTP_WRITE 0xC200000B 47*91f16700Schasinglulu 48*91f16700Schasinglulu #define IMX_SIP_MISC_SET_TEMP 0xC200000C 49*91f16700Schasinglulu 50*91f16700Schasinglulu #define IMX_SIP_AARCH32 0xC20000FD 51*91f16700Schasinglulu 52*91f16700Schasinglulu int imx_kernel_entry_handler(uint32_t smc_fid, u_register_t x1, 53*91f16700Schasinglulu u_register_t x2, u_register_t x3, 54*91f16700Schasinglulu u_register_t x4); 55*91f16700Schasinglulu #if defined(PLAT_imx8mq) 56*91f16700Schasinglulu int imx_soc_info_handler(uint32_t smc_fid, u_register_t x1, 57*91f16700Schasinglulu u_register_t x2, u_register_t x3); 58*91f16700Schasinglulu int imx_gpc_handler(uint32_t smc_fid, u_register_t x1, 59*91f16700Schasinglulu u_register_t x2, u_register_t x3); 60*91f16700Schasinglulu int dram_dvfs_handler(uint32_t smc_fid, void *handle, 61*91f16700Schasinglulu u_register_t x1, u_register_t x2, u_register_t x3); 62*91f16700Schasinglulu #endif 63*91f16700Schasinglulu #if defined(PLAT_imx8mm) || defined(PLAT_imx8mn) || defined(PLAT_imx8mp) 64*91f16700Schasinglulu int dram_dvfs_handler(uint32_t smc_fid, void *handle, 65*91f16700Schasinglulu u_register_t x1, u_register_t x2, u_register_t x3); 66*91f16700Schasinglulu 67*91f16700Schasinglulu int imx_gpc_handler(uint32_t smc_fid, u_register_t x1, 68*91f16700Schasinglulu u_register_t x2, u_register_t x3); 69*91f16700Schasinglulu #endif 70*91f16700Schasinglulu 71*91f16700Schasinglulu #if defined(PLAT_imx8mm) || defined(PLAT_imx8mq) 72*91f16700Schasinglulu int imx_src_handler(uint32_t smc_fid, u_register_t x1, 73*91f16700Schasinglulu u_register_t x2, u_register_t x3, void *handle); 74*91f16700Schasinglulu #endif 75*91f16700Schasinglulu 76*91f16700Schasinglulu #if defined(PLAT_imx8mm) || defined(PLAT_imx8mn) || defined(PLAT_imx8mp) 77*91f16700Schasinglulu int imx_hab_handler(uint32_t smc_fid, u_register_t x1, 78*91f16700Schasinglulu u_register_t x2, u_register_t x3, u_register_t x4); 79*91f16700Schasinglulu #endif 80*91f16700Schasinglulu 81*91f16700Schasinglulu #if (defined(PLAT_imx8qm) || defined(PLAT_imx8qx)) 82*91f16700Schasinglulu int imx_cpufreq_handler(uint32_t smc_fid, u_register_t x1, 83*91f16700Schasinglulu u_register_t x2, u_register_t x3); 84*91f16700Schasinglulu int imx_srtc_handler(uint32_t smc_fid, void *handle, u_register_t x1, 85*91f16700Schasinglulu u_register_t x2, u_register_t x3, u_register_t x4); 86*91f16700Schasinglulu int imx_wakeup_src_handler(uint32_t smc_fid, u_register_t x1, 87*91f16700Schasinglulu u_register_t x2, u_register_t x3); 88*91f16700Schasinglulu int imx_otp_handler(uint32_t smc_fid, void *handle, 89*91f16700Schasinglulu u_register_t x1, u_register_t x2); 90*91f16700Schasinglulu int imx_misc_set_temp_handler(uint32_t smc_fid, u_register_t x1, 91*91f16700Schasinglulu u_register_t x2, u_register_t x3, 92*91f16700Schasinglulu u_register_t x4); 93*91f16700Schasinglulu #endif 94*91f16700Schasinglulu uint64_t imx_buildinfo_handler(uint32_t smc_fid, u_register_t x1, 95*91f16700Schasinglulu u_register_t x2, u_register_t x3, 96*91f16700Schasinglulu u_register_t x4); 97*91f16700Schasinglulu 98*91f16700Schasinglulu #endif /* __IMX_SIP_SVC_H__ */ 99