xref: /arm-trusted-firmware/plat/imx/common/imx_sip_svc.c (revision 91f16700b400a8c0651d24a598fc48ee2997a0d7)
1*91f16700Schasinglulu /*
2*91f16700Schasinglulu  * Copyright (c) 2015-2023, ARM Limited and Contributors. All rights reserved.
3*91f16700Schasinglulu  *
4*91f16700Schasinglulu  * SPDX-License-Identifier: BSD-3-Clause
5*91f16700Schasinglulu  */
6*91f16700Schasinglulu 
7*91f16700Schasinglulu #include <stdint.h>
8*91f16700Schasinglulu #include <common/debug.h>
9*91f16700Schasinglulu #include <common/runtime_svc.h>
10*91f16700Schasinglulu #include <lib/pmf/pmf.h>
11*91f16700Schasinglulu #include <tools_share/uuid.h>
12*91f16700Schasinglulu #include <imx_sip_svc.h>
13*91f16700Schasinglulu 
14*91f16700Schasinglulu static int32_t imx_sip_setup(void)
15*91f16700Schasinglulu {
16*91f16700Schasinglulu 	return 0;
17*91f16700Schasinglulu }
18*91f16700Schasinglulu 
19*91f16700Schasinglulu static uintptr_t imx_sip_handler(unsigned int smc_fid,
20*91f16700Schasinglulu 			u_register_t x1,
21*91f16700Schasinglulu 			u_register_t x2,
22*91f16700Schasinglulu 			u_register_t x3,
23*91f16700Schasinglulu 			u_register_t x4,
24*91f16700Schasinglulu 			void *cookie,
25*91f16700Schasinglulu 			void *handle,
26*91f16700Schasinglulu 			u_register_t flags)
27*91f16700Schasinglulu {
28*91f16700Schasinglulu 	switch (smc_fid) {
29*91f16700Schasinglulu 	case IMX_SIP_AARCH32:
30*91f16700Schasinglulu 		SMC_RET1(handle, imx_kernel_entry_handler(smc_fid, x1, x2, x3, x4));
31*91f16700Schasinglulu 		break;
32*91f16700Schasinglulu #if defined(PLAT_imx8mq)
33*91f16700Schasinglulu 	case IMX_SIP_GET_SOC_INFO:
34*91f16700Schasinglulu 		SMC_RET1(handle, imx_soc_info_handler(smc_fid, x1, x2, x3));
35*91f16700Schasinglulu 		break;
36*91f16700Schasinglulu 	case IMX_SIP_GPC:
37*91f16700Schasinglulu 		SMC_RET1(handle, imx_gpc_handler(smc_fid, x1, x2, x3));
38*91f16700Schasinglulu 		break;
39*91f16700Schasinglulu 	case IMX_SIP_DDR_DVFS:
40*91f16700Schasinglulu 		return dram_dvfs_handler(smc_fid, handle, x1, x2, x3);
41*91f16700Schasinglulu #endif
42*91f16700Schasinglulu #if defined(PLAT_imx8mm) || defined(PLAT_imx8mn) || defined(PLAT_imx8mp)
43*91f16700Schasinglulu 	case IMX_SIP_DDR_DVFS:
44*91f16700Schasinglulu 		return dram_dvfs_handler(smc_fid, handle, x1, x2, x3);
45*91f16700Schasinglulu 	case IMX_SIP_GPC:
46*91f16700Schasinglulu 		SMC_RET1(handle, imx_gpc_handler(smc_fid, x1, x2, x3));
47*91f16700Schasinglulu 		break;
48*91f16700Schasinglulu #endif
49*91f16700Schasinglulu #if (defined(PLAT_imx8qm) || defined(PLAT_imx8qx))
50*91f16700Schasinglulu 	case  IMX_SIP_SRTC:
51*91f16700Schasinglulu 		return imx_srtc_handler(smc_fid, handle, x1, x2, x3, x4);
52*91f16700Schasinglulu 	case  IMX_SIP_CPUFREQ:
53*91f16700Schasinglulu 		SMC_RET1(handle, imx_cpufreq_handler(smc_fid, x1, x2, x3));
54*91f16700Schasinglulu 		break;
55*91f16700Schasinglulu 	case  IMX_SIP_WAKEUP_SRC:
56*91f16700Schasinglulu 		SMC_RET1(handle, imx_wakeup_src_handler(smc_fid, x1, x2, x3));
57*91f16700Schasinglulu 	case IMX_SIP_OTP_READ:
58*91f16700Schasinglulu 	case IMX_SIP_OTP_WRITE:
59*91f16700Schasinglulu 		return imx_otp_handler(smc_fid, handle, x1, x2);
60*91f16700Schasinglulu 	case IMX_SIP_MISC_SET_TEMP:
61*91f16700Schasinglulu 		SMC_RET1(handle, imx_misc_set_temp_handler(smc_fid, x1, x2, x3, x4));
62*91f16700Schasinglulu #endif
63*91f16700Schasinglulu #if defined(PLAT_imx8mm) || defined(PLAT_imx8mq)
64*91f16700Schasinglulu 	case IMX_SIP_SRC:
65*91f16700Schasinglulu 		SMC_RET1(handle, imx_src_handler(smc_fid, x1, x2, x3, handle));
66*91f16700Schasinglulu 		break;
67*91f16700Schasinglulu #endif
68*91f16700Schasinglulu #if defined(PLAT_imx8mm) || defined(PLAT_imx8mn) || defined(PLAT_imx8mp)
69*91f16700Schasinglulu 	case IMX_SIP_HAB:
70*91f16700Schasinglulu 		SMC_RET1(handle, imx_hab_handler(smc_fid, x1, x2, x3, x4));
71*91f16700Schasinglulu 		break;
72*91f16700Schasinglulu #endif
73*91f16700Schasinglulu 	case  IMX_SIP_BUILDINFO:
74*91f16700Schasinglulu 		SMC_RET1(handle, imx_buildinfo_handler(smc_fid, x1, x2, x3, x4));
75*91f16700Schasinglulu 	default:
76*91f16700Schasinglulu 		WARN("Unimplemented i.MX SiP Service Call: 0x%x\n", smc_fid);
77*91f16700Schasinglulu 		SMC_RET1(handle, SMC_UNK);
78*91f16700Schasinglulu 		break;
79*91f16700Schasinglulu 	}
80*91f16700Schasinglulu }
81*91f16700Schasinglulu 
82*91f16700Schasinglulu /* Define a runtime service descriptor for fast SMC calls */
83*91f16700Schasinglulu DECLARE_RT_SVC(
84*91f16700Schasinglulu 		imx_sip_svc,
85*91f16700Schasinglulu 		OEN_SIP_START,
86*91f16700Schasinglulu 		OEN_SIP_END,
87*91f16700Schasinglulu 		SMC_TYPE_FAST,
88*91f16700Schasinglulu 		imx_sip_setup,
89*91f16700Schasinglulu 		imx_sip_handler
90*91f16700Schasinglulu );
91