1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #include <lib/mmio.h> 8*91f16700Schasinglulu #include <lib/utils_def.h> 9*91f16700Schasinglulu 10*91f16700Schasinglulu #include <imx_aips.h> 11*91f16700Schasinglulu #include <imx_regs.h> 12*91f16700Schasinglulu 13*91f16700Schasinglulu static void imx_aips_set_default_access(struct aipstz_regs *aips_regs) 14*91f16700Schasinglulu { 15*91f16700Schasinglulu int i; 16*91f16700Schasinglulu uintptr_t addr; 17*91f16700Schasinglulu 18*91f16700Schasinglulu /* 19*91f16700Schasinglulu * See section 4.7.7.1 AIPSTZ_MPR field descriptions 20*91f16700Schasinglulu * i.MX 7Solo Applications Processor Reference Manual, Rev. 0.1, 08/2016 21*91f16700Schasinglulu * 0111 -> 22*91f16700Schasinglulu * 0: Write Access from master not buffered 23*91f16700Schasinglulu * 1: Master is trusted for read access 24*91f16700Schasinglulu * 1: Master is trsuted for write access 25*91f16700Schasinglulu * 1: Access from master is not forced to user mode 26*91f16700Schasinglulu */ 27*91f16700Schasinglulu addr = (uintptr_t)&aips_regs->aipstz_mpr; 28*91f16700Schasinglulu mmio_write_32(addr, 0x77777777); 29*91f16700Schasinglulu 30*91f16700Schasinglulu /* 31*91f16700Schasinglulu * Helpfully the OPACR registers have the logical inversion of the above 32*91f16700Schasinglulu * See section 4.7.7.1 AIPSTZ_MPR field descriptions 33*91f16700Schasinglulu * i.MX 7Solo Applications Processor Reference Manual, Rev. 0.1, 08/2016 34*91f16700Schasinglulu * 0000 -> 35*91f16700Schasinglulu * 0: Write Access to the peripheral is not buffered by AIPSTZ 36*91f16700Schasinglulu * 0: The peripheral does not require supervisor priv to access 37*91f16700Schasinglulu * 0: Master is trsuted for write access 38*91f16700Schasinglulu * 0: Access from master is not forced to user mode 39*91f16700Schasinglulu */ 40*91f16700Schasinglulu for (i = 0; i < AIPSTZ_OAPCR_COUNT; i++) { 41*91f16700Schasinglulu addr = (uintptr_t)&aips_regs->aipstz_opacr[i]; 42*91f16700Schasinglulu mmio_write_32(addr, 0x00000000); 43*91f16700Schasinglulu } 44*91f16700Schasinglulu } 45*91f16700Schasinglulu 46*91f16700Schasinglulu void imx_aips_init(void) 47*91f16700Schasinglulu { 48*91f16700Schasinglulu int i; 49*91f16700Schasinglulu struct aipstz_regs *aips_regs[] = { 50*91f16700Schasinglulu (struct aipstz_regs *)(AIPS1_BASE + AIPSTZ_CONFIG_OFFSET), 51*91f16700Schasinglulu (struct aipstz_regs *)(AIPS2_BASE + AIPSTZ_CONFIG_OFFSET), 52*91f16700Schasinglulu (struct aipstz_regs *)(AIPS3_BASE + AIPSTZ_CONFIG_OFFSET), 53*91f16700Schasinglulu }; 54*91f16700Schasinglulu 55*91f16700Schasinglulu for (i = 0; i < ARRAY_SIZE(aips_regs); i++) 56*91f16700Schasinglulu imx_aips_set_default_access(aips_regs[i]); 57*91f16700Schasinglulu } 58