1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #include <stdbool.h> 8*91f16700Schasinglulu 9*91f16700Schasinglulu #include <arch.h> 10*91f16700Schasinglulu #include <arch_helpers.h> 11*91f16700Schasinglulu #include <common/debug.h> 12*91f16700Schasinglulu 13*91f16700Schasinglulu #include <plat_imx8.h> 14*91f16700Schasinglulu #include <sci/sci.h> 15*91f16700Schasinglulu 16*91f16700Schasinglulu void __dead2 imx_system_off(void) 17*91f16700Schasinglulu { 18*91f16700Schasinglulu sc_pm_set_sys_power_mode(ipc_handle, SC_PM_PW_MODE_OFF); 19*91f16700Schasinglulu wfi(); 20*91f16700Schasinglulu ERROR("power off failed.\n"); 21*91f16700Schasinglulu panic(); 22*91f16700Schasinglulu } 23*91f16700Schasinglulu 24*91f16700Schasinglulu void __dead2 imx_system_reset(void) 25*91f16700Schasinglulu { 26*91f16700Schasinglulu sc_pm_reset(ipc_handle, SC_PM_RESET_TYPE_BOARD); 27*91f16700Schasinglulu wfi(); 28*91f16700Schasinglulu ERROR("system reset failed.\n"); 29*91f16700Schasinglulu panic(); 30*91f16700Schasinglulu } 31*91f16700Schasinglulu 32*91f16700Schasinglulu int imx_validate_power_state(unsigned int power_state, 33*91f16700Schasinglulu psci_power_state_t *req_state) 34*91f16700Schasinglulu { 35*91f16700Schasinglulu int pwr_lvl = psci_get_pstate_pwrlvl(power_state); 36*91f16700Schasinglulu int pwr_type = psci_get_pstate_type(power_state); 37*91f16700Schasinglulu int state_id = psci_get_pstate_id(power_state); 38*91f16700Schasinglulu 39*91f16700Schasinglulu if (pwr_lvl > PLAT_MAX_PWR_LVL) 40*91f16700Schasinglulu return PSCI_E_INVALID_PARAMS; 41*91f16700Schasinglulu 42*91f16700Schasinglulu if (pwr_type == PSTATE_TYPE_POWERDOWN) { 43*91f16700Schasinglulu req_state->pwr_domain_state[MPIDR_AFFLVL0] = PLAT_MAX_OFF_STATE; 44*91f16700Schasinglulu if (!state_id) 45*91f16700Schasinglulu req_state->pwr_domain_state[MPIDR_AFFLVL1] = PLAT_MAX_RET_STATE; 46*91f16700Schasinglulu else 47*91f16700Schasinglulu req_state->pwr_domain_state[MPIDR_AFFLVL1] = PLAT_MAX_OFF_STATE; 48*91f16700Schasinglulu } 49*91f16700Schasinglulu 50*91f16700Schasinglulu return PSCI_E_SUCCESS; 51*91f16700Schasinglulu } 52*91f16700Schasinglulu 53*91f16700Schasinglulu void imx_get_sys_suspend_power_state(psci_power_state_t *req_state) 54*91f16700Schasinglulu { 55*91f16700Schasinglulu unsigned int i; 56*91f16700Schasinglulu 57*91f16700Schasinglulu /* CPU & cluster off, system in retention */ 58*91f16700Schasinglulu for (i = MPIDR_AFFLVL0; i < PLAT_MAX_PWR_LVL; i++) 59*91f16700Schasinglulu req_state->pwr_domain_state[i] = PLAT_MAX_OFF_STATE; 60*91f16700Schasinglulu req_state->pwr_domain_state[PLAT_MAX_PWR_LVL] = PLAT_MAX_RET_STATE; 61*91f16700Schasinglulu } 62*91f16700Schasinglulu 63