1*91f16700Schasinglulu/* 2*91f16700Schasinglulu * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu#include <asm_macros.S> 8*91f16700Schasinglulu#include <platform_def.h> 9*91f16700Schasinglulu#include <cortex_a35.h> 10*91f16700Schasinglulu 11*91f16700Schasinglulu .globl plat_is_my_cpu_primary 12*91f16700Schasinglulu .globl plat_my_core_pos 13*91f16700Schasinglulu .globl plat_calc_core_pos 14*91f16700Schasinglulu .globl plat_reset_handler 15*91f16700Schasinglulu .globl plat_get_my_entrypoint 16*91f16700Schasinglulu .globl plat_secondary_cold_boot_setup 17*91f16700Schasinglulu .globl plat_crash_console_init 18*91f16700Schasinglulu .globl plat_crash_console_putc 19*91f16700Schasinglulu .globl plat_crash_console_flush 20*91f16700Schasinglulu .globl platform_mem_init 21*91f16700Schasinglulu .globl imx_mailbox_init 22*91f16700Schasinglulu 23*91f16700Schasinglulu /* -------------------------------------------------------------------- 24*91f16700Schasinglulu * Helper macro that reads the part number of the current CPU and jumps 25*91f16700Schasinglulu * to the given label if it matches the CPU MIDR provided. 26*91f16700Schasinglulu * 27*91f16700Schasinglulu * Clobbers x0. 28*91f16700Schasinglulu * -------------------------------------------------------------------- 29*91f16700Schasinglulu */ 30*91f16700Schasinglulu .macro jump_if_cpu_midr _cpu_midr, _label 31*91f16700Schasinglulu 32*91f16700Schasinglulu mrs x0, midr_el1 33*91f16700Schasinglulu ubfx x0, x0, MIDR_PN_SHIFT, #12 34*91f16700Schasinglulu cmp w0, #((\_cpu_midr >> MIDR_PN_SHIFT) & MIDR_PN_MASK) 35*91f16700Schasinglulu b.eq \_label 36*91f16700Schasinglulu 37*91f16700Schasinglulu .endm 38*91f16700Schasinglulu 39*91f16700Schasinglulu /* ---------------------------------------------- 40*91f16700Schasinglulu * The mailbox_base is used to distinguish warm/cold 41*91f16700Schasinglulu * reset. The mailbox_base is in the data section, not 42*91f16700Schasinglulu * in .bss, this allows function to start using this 43*91f16700Schasinglulu * variable before the runtime memory is initialized. 44*91f16700Schasinglulu * ---------------------------------------------- 45*91f16700Schasinglulu */ 46*91f16700Schasinglulu .section .data.mailbox_base 47*91f16700Schasinglulu .align 3 48*91f16700Schasinglulu mailbox_base: .quad 0x0 49*91f16700Schasinglulu 50*91f16700Schasinglulu /* ---------------------------------------------- 51*91f16700Schasinglulu * unsigned int plat_is_my_cpu_primary(void); 52*91f16700Schasinglulu * This function checks if this is the primary CPU 53*91f16700Schasinglulu * ---------------------------------------------- 54*91f16700Schasinglulu */ 55*91f16700Schasinglulufunc plat_is_my_cpu_primary 56*91f16700Schasinglulu mrs x0, mpidr_el1 57*91f16700Schasinglulu and x0, x0, #(MPIDR_CPU_MASK) 58*91f16700Schasinglulu cmp x0, #PLAT_PRIMARY_CPU 59*91f16700Schasinglulu cset x0, eq 60*91f16700Schasinglulu ret 61*91f16700Schasingluluendfunc plat_is_my_cpu_primary 62*91f16700Schasinglulu 63*91f16700Schasinglulu /* ---------------------------------------------- 64*91f16700Schasinglulu * unsigned int plat_my_core_pos(void) 65*91f16700Schasinglulu * This Function uses the plat_calc_core_pos() 66*91f16700Schasinglulu * to get the index of the calling CPU. 67*91f16700Schasinglulu * ---------------------------------------------- 68*91f16700Schasinglulu */ 69*91f16700Schasinglulufunc plat_my_core_pos 70*91f16700Schasinglulu mrs x0, mpidr_el1 71*91f16700Schasinglulu and x1, x0, #MPIDR_CPU_MASK 72*91f16700Schasinglulu and x0, x0, #MPIDR_CLUSTER_MASK 73*91f16700Schasinglulu add x0, x1, x0, LSR #6 74*91f16700Schasinglulu ret 75*91f16700Schasingluluendfunc plat_my_core_pos 76*91f16700Schasinglulu 77*91f16700Schasinglulu /* 78*91f16700Schasinglulu * unsigned int plat_calc_core_pos(uint64_t mpidr) 79*91f16700Schasinglulu * helper function to calculate the core position. 80*91f16700Schasinglulu * With this function. 81*91f16700Schasinglulu */ 82*91f16700Schasinglulufunc plat_calc_core_pos 83*91f16700Schasinglulu and x1, x0, #MPIDR_CPU_MASK 84*91f16700Schasinglulu and x0, x0, #MPIDR_CLUSTER_MASK 85*91f16700Schasinglulu add x0, x1, x0, LSR #6 86*91f16700Schasinglulu ret 87*91f16700Schasingluluendfunc plat_calc_core_pos 88*91f16700Schasinglulu 89*91f16700Schasinglulu /* --------------------------------------------- 90*91f16700Schasinglulu * function to get the entrypoint. 91*91f16700Schasinglulu * --------------------------------------------- 92*91f16700Schasinglulu */ 93*91f16700Schasinglulufunc plat_get_my_entrypoint 94*91f16700Schasinglulu adrp x1, mailbox_base 95*91f16700Schasinglulu ldr x0, [x1, :lo12:mailbox_base] 96*91f16700Schasinglulu ret 97*91f16700Schasingluluendfunc plat_get_my_entrypoint 98*91f16700Schasinglulu 99*91f16700Schasinglulufunc imx_mailbox_init 100*91f16700Schasinglulu adrp x1, mailbox_base 101*91f16700Schasinglulu str x0, [x1, :lo12:mailbox_base] 102*91f16700Schasinglulu ret 103*91f16700Schasingluluendfunc imx_mailbox_init 104*91f16700Schasinglulu 105*91f16700Schasinglulufunc plat_secondary_cold_boot_setup 106*91f16700Schasinglulu b . 107*91f16700Schasingluluendfunc plat_secondary_cold_boot_setup 108*91f16700Schasinglulu 109*91f16700Schasinglulufunc plat_crash_console_init 110*91f16700Schasinglulu mov x0, #1 111*91f16700Schasinglulu ret 112*91f16700Schasingluluendfunc plat_crash_console_init 113*91f16700Schasinglulu 114*91f16700Schasinglulufunc plat_crash_console_putc 115*91f16700Schasinglulu ret 116*91f16700Schasingluluendfunc plat_crash_console_putc 117*91f16700Schasinglulu 118*91f16700Schasinglulufunc plat_crash_console_flush 119*91f16700Schasinglulu mov x0, #0 120*91f16700Schasinglulu ret 121*91f16700Schasingluluendfunc plat_crash_console_flush 122*91f16700Schasinglulu 123*91f16700Schasinglulufunc platform_mem_init 124*91f16700Schasinglulu ret 125*91f16700Schasingluluendfunc platform_mem_init 126