1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2022-2023, ARM Limited and Contributors. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #ifndef SIGI_DEF_H 8*91f16700Schasinglulu #define SIGI_DEF_H 9*91f16700Schasinglulu 10*91f16700Schasinglulu #include <stdint.h> 11*91f16700Schasinglulu 12*91f16700Schasinglulu #define PLATFORM_NAME "hobot sigi virt platform" 13*91f16700Schasinglulu 14*91f16700Schasinglulu /* Clock configuration */ 15*91f16700Schasinglulu #define SIGI_OSC24M_CLK_IN_HZ 24000000 16*91f16700Schasinglulu 17*91f16700Schasinglulu /* UART configuration */ 18*91f16700Schasinglulu #define SIGI_UART0_BAUDRATE 115200 19*91f16700Schasinglulu #define SIGI_UART0_CLK_IN_HZ SIGI_OSC24M_CLK_IN_HZ 20*91f16700Schasinglulu 21*91f16700Schasinglulu unsigned int sigi_calc_core_pos(u_register_t mpidr); 22*91f16700Schasinglulu void sigi_console_init(void); 23*91f16700Schasinglulu void plat_sigi_gic_init(void); 24*91f16700Schasinglulu void sigi_pwr_gic_on_finish(void); 25*91f16700Schasinglulu void sigi_pwr_gic_off(void); 26*91f16700Schasinglulu 27*91f16700Schasinglulu /* PMU register offsets for CPU*/ 28*91f16700Schasinglulu enum { 29*91f16700Schasinglulu CPU_CL0_C0_0 = 0x0214, 30*91f16700Schasinglulu CPU_CL0_C0_1 = 0x0218, 31*91f16700Schasinglulu CPU_CL0_C1_0 = 0x0220, 32*91f16700Schasinglulu CPU_CL0_C1_1 = 0x0224, 33*91f16700Schasinglulu CPU_CL0_C2_0 = 0x022c, 34*91f16700Schasinglulu CPU_CL0_C2_1 = 0x0230, 35*91f16700Schasinglulu CPU_CL0_C3_0 = 0x0238, 36*91f16700Schasinglulu CPU_CL0_C3_1 = 0x023c, 37*91f16700Schasinglulu CPU_CL1_C0_0 = 0x0240, 38*91f16700Schasinglulu CPU_CL1_C0_1 = 0x0244, 39*91f16700Schasinglulu CPU_CL1_C1_0 = 0x0248, 40*91f16700Schasinglulu CPU_CL1_C1_1 = 0x024c, 41*91f16700Schasinglulu }; 42*91f16700Schasinglulu 43*91f16700Schasinglulu #define SIGI_PMU_BASE 0x23190000U 44*91f16700Schasinglulu 45*91f16700Schasinglulu #endif /* SIGI_DEF_H */