1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu #ifndef HI3660_HKADC_H 7*91f16700Schasinglulu #define HI3660_HKADC_H 8*91f16700Schasinglulu 9*91f16700Schasinglulu #define HKADC_SSI_REG_BASE 0xE82B8000 10*91f16700Schasinglulu 11*91f16700Schasinglulu #define HKADC_DSP_START_REG (HKADC_SSI_REG_BASE + 0x000) 12*91f16700Schasinglulu #define HKADC_WR_NUM_REG (HKADC_SSI_REG_BASE + 0x008) 13*91f16700Schasinglulu #define HKADC_DSP_START_CLR_REG (HKADC_SSI_REG_BASE + 0x01C) 14*91f16700Schasinglulu #define HKADC_WR01_DATA_REG (HKADC_SSI_REG_BASE + 0x020) 15*91f16700Schasinglulu 16*91f16700Schasinglulu #define WR1_WRITE_MODE (1U << 31) 17*91f16700Schasinglulu #define WR1_READ_MODE (0 << 31) 18*91f16700Schasinglulu #define WR1_ADDR(x) (((x) & 0x7F) << 24) 19*91f16700Schasinglulu #define WR1_DATA(x) (((x) & 0xFF) << 16) 20*91f16700Schasinglulu #define WR0_WRITE_MODE (1 << 15) 21*91f16700Schasinglulu #define WR0_READ_MODE (0 << 15) 22*91f16700Schasinglulu #define WR0_ADDR(x) (((x) & 0x7F) << 8) 23*91f16700Schasinglulu #define WR0_DATA(x) ((x) & 0xFF) 24*91f16700Schasinglulu 25*91f16700Schasinglulu #define HKADC_WR23_DATA_REG (HKADC_SSI_REG_BASE + 0x024) 26*91f16700Schasinglulu #define HKADC_WR45_DATA_REG (HKADC_SSI_REG_BASE + 0x028) 27*91f16700Schasinglulu #define HKADC_DELAY01_REG (HKADC_SSI_REG_BASE + 0x030) 28*91f16700Schasinglulu #define HKADC_DELAY23_REG (HKADC_SSI_REG_BASE + 0x034) 29*91f16700Schasinglulu #define HKADC_DELAY45_REG (HKADC_SSI_REG_BASE + 0x038) 30*91f16700Schasinglulu #define HKADC_DSP_RD2_DATA_REG (HKADC_SSI_REG_BASE + 0x048) 31*91f16700Schasinglulu #define HKADC_DSP_RD3_DATA_REG (HKADC_SSI_REG_BASE + 0x04C) 32*91f16700Schasinglulu 33*91f16700Schasinglulu /* HKADC Internal Registers */ 34*91f16700Schasinglulu #define HKADC_CTRL_ADDR 0x00 35*91f16700Schasinglulu #define HKADC_START_ADDR 0x01 36*91f16700Schasinglulu #define HKADC_DATA1_ADDR 0x03 /* high 8 bits */ 37*91f16700Schasinglulu #define HKADC_DATA0_ADDR 0x04 /* low 8 bits */ 38*91f16700Schasinglulu #define HKADC_MODE_CFG 0x0A 39*91f16700Schasinglulu 40*91f16700Schasinglulu #define HKADC_VALUE_HIGH 0x0FF0 41*91f16700Schasinglulu #define HKADC_VALUE_LOW 0x000F 42*91f16700Schasinglulu #define HKADC_VALID_VALUE 0x0FFF 43*91f16700Schasinglulu 44*91f16700Schasinglulu #define HKADC_CHANNEL_MAX 15 45*91f16700Schasinglulu #define HKADC_VREF_1V8 1800 46*91f16700Schasinglulu #define HKADC_ACCURACY 0x0FFF 47*91f16700Schasinglulu 48*91f16700Schasinglulu #define HKADC_WR01_VALUE ((HKADC_START_ADDR << 24) | \ 49*91f16700Schasinglulu (0x1 << 16)) 50*91f16700Schasinglulu #define HKADC_WR23_VALUE ((0x1u << 31) | \ 51*91f16700Schasinglulu (HKADC_DATA0_ADDR << 24) | \ 52*91f16700Schasinglulu (1 << 15) | \ 53*91f16700Schasinglulu (HKADC_DATA1_ADDR << 8)) 54*91f16700Schasinglulu #define HKADC_WR45_VALUE (0x80) 55*91f16700Schasinglulu #define HKADC_CHANNEL0_DELAY01_VALUE ((0x0700 << 16) | 0xFFFF) 56*91f16700Schasinglulu #define HKADC_DELAY01_VALUE ((0x0700 << 16) | 0x0200) 57*91f16700Schasinglulu #define HKADC_DELAY23_VALUE ((0x00C8 << 16) | 0x00C8) 58*91f16700Schasinglulu #define START_DELAY_TIMEOUT 2000 59*91f16700Schasinglulu #define HKADC_WR_NUM_VALUE 4 60*91f16700Schasinglulu 61*91f16700Schasinglulu #endif /* HI3660_HKADC_H */ 62