1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #ifndef PLATFORM_DEF_H 8*91f16700Schasinglulu #define PLATFORM_DEF_H 9*91f16700Schasinglulu 10*91f16700Schasinglulu #include <arch.h> 11*91f16700Schasinglulu #include <common/tbbr/tbbr_img_def.h> 12*91f16700Schasinglulu #include <lib/utils_def.h> 13*91f16700Schasinglulu #include <plat/common/common_def.h> 14*91f16700Schasinglulu 15*91f16700Schasinglulu #include <hikey_def.h> 16*91f16700Schasinglulu #include <hikey_layout.h> /* BL memory region sizes, etc */ 17*91f16700Schasinglulu 18*91f16700Schasinglulu /* Special value used to verify platform parameters from BL2 to BL3-1 */ 19*91f16700Schasinglulu #define HIKEY_BL31_PLAT_PARAM_VAL 0x0f1e2d3c4b5a6978ULL 20*91f16700Schasinglulu 21*91f16700Schasinglulu /* 22*91f16700Schasinglulu * Generic platform constants 23*91f16700Schasinglulu */ 24*91f16700Schasinglulu 25*91f16700Schasinglulu /* Size of cacheable stacks */ 26*91f16700Schasinglulu #define PLATFORM_STACK_SIZE 0x1000 27*91f16700Schasinglulu 28*91f16700Schasinglulu #define FIRMWARE_WELCOME_STR "Booting Trusted Firmware\n" 29*91f16700Schasinglulu 30*91f16700Schasinglulu #define PLATFORM_CACHE_LINE_SIZE 64 31*91f16700Schasinglulu #define PLATFORM_CLUSTER_COUNT U(2) 32*91f16700Schasinglulu #define PLATFORM_CORE_COUNT_PER_CLUSTER U(4) 33*91f16700Schasinglulu #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER_COUNT * \ 34*91f16700Schasinglulu PLATFORM_CORE_COUNT_PER_CLUSTER) 35*91f16700Schasinglulu #define PLAT_MAX_PWR_LVL (MPIDR_AFFLVL2) 36*91f16700Schasinglulu #define PLAT_NUM_PWR_DOMAINS (PLATFORM_CORE_COUNT + \ 37*91f16700Schasinglulu PLATFORM_CLUSTER_COUNT + U(1)) 38*91f16700Schasinglulu 39*91f16700Schasinglulu #define PLAT_MAX_RET_STATE U(1) 40*91f16700Schasinglulu #define PLAT_MAX_OFF_STATE U(2) 41*91f16700Schasinglulu 42*91f16700Schasinglulu #define MAX_IO_DEVICES 3 43*91f16700Schasinglulu #define MAX_IO_HANDLES 4 44*91f16700Schasinglulu /* eMMC RPMB and eMMC User Data */ 45*91f16700Schasinglulu #define MAX_IO_BLOCK_DEVICES U(2) 46*91f16700Schasinglulu 47*91f16700Schasinglulu /* GIC related constants (no GICR in GIC-400) */ 48*91f16700Schasinglulu #define PLAT_ARM_GICD_BASE 0xF6801000 49*91f16700Schasinglulu #define PLAT_ARM_GICC_BASE 0xF6802000 50*91f16700Schasinglulu #define PLAT_ARM_GICH_BASE 0xF6804000 51*91f16700Schasinglulu #define PLAT_ARM_GICV_BASE 0xF6806000 52*91f16700Schasinglulu 53*91f16700Schasinglulu /* 54*91f16700Schasinglulu * Platform specific page table and MMU setup constants 55*91f16700Schasinglulu */ 56*91f16700Schasinglulu #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) 57*91f16700Schasinglulu #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) 58*91f16700Schasinglulu 59*91f16700Schasinglulu #if defined(IMAGE_BL1) || defined(IMAGE_BL32) 60*91f16700Schasinglulu #define MAX_XLAT_TABLES 3 61*91f16700Schasinglulu #endif 62*91f16700Schasinglulu 63*91f16700Schasinglulu #ifdef IMAGE_BL31 64*91f16700Schasinglulu #define MAX_XLAT_TABLES 4 65*91f16700Schasinglulu #endif 66*91f16700Schasinglulu 67*91f16700Schasinglulu #ifdef IMAGE_BL2 68*91f16700Schasinglulu #define MAX_XLAT_TABLES 4 69*91f16700Schasinglulu #endif 70*91f16700Schasinglulu 71*91f16700Schasinglulu #define MAX_MMAP_REGIONS 16 72*91f16700Schasinglulu 73*91f16700Schasinglulu /* 74*91f16700Schasinglulu * Declarations and constants to access the mailboxes safely. Each mailbox is 75*91f16700Schasinglulu * aligned on the biggest cache line size in the platform. This is known only 76*91f16700Schasinglulu * to the platform as it might have a combination of integrated and external 77*91f16700Schasinglulu * caches. Such alignment ensures that two maiboxes do not sit on the same cache 78*91f16700Schasinglulu * line at any cache level. They could belong to different cpus/clusters & 79*91f16700Schasinglulu * get written while being protected by different locks causing corruption of 80*91f16700Schasinglulu * a valid mailbox address. 81*91f16700Schasinglulu */ 82*91f16700Schasinglulu #define CACHE_WRITEBACK_SHIFT 6 83*91f16700Schasinglulu #define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) 84*91f16700Schasinglulu 85*91f16700Schasinglulu #endif /* PLATFORM_DEF_H */ 86