1*91f16700Schasinglulu/* 2*91f16700Schasinglulu * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu#ifndef PLAT_MACROS_S 8*91f16700Schasinglulu#define PLAT_MACROS_S 9*91f16700Schasinglulu 10*91f16700Schasinglulu#include <drivers/arm/cci.h> 11*91f16700Schasinglulu#include <drivers/arm/gicv2.h> 12*91f16700Schasinglulu#include <hi6220.h> 13*91f16700Schasinglulu#include <platform_def.h> 14*91f16700Schasinglulu 15*91f16700Schasinglulu.section .rodata.gic_reg_name, "aS" 16*91f16700Schasinglulugicc_regs: 17*91f16700Schasinglulu .asciz "gicc_hppir", "gicc_ahppir", "gicc_ctlr", "" 18*91f16700Schasinglulugicd_pend_reg: 19*91f16700Schasinglulu .asciz "gicd_ispendr regs (Offsets 0x200 - 0x278)\n Offset:\t\t\tvalue\n" 20*91f16700Schasinglulunewline: 21*91f16700Schasinglulu .asciz "\n" 22*91f16700Schasingluluspacer: 23*91f16700Schasinglulu .asciz ":\t\t0x" 24*91f16700Schasinglulu 25*91f16700Schasinglulu.section .rodata.cci_reg_name, "aS" 26*91f16700Schasinglulucci_iface_regs: 27*91f16700Schasinglulu .asciz "cci_snoop_ctrl_cluster0", "cci_snoop_ctrl_cluster1" , "" 28*91f16700Schasinglulu 29*91f16700Schasinglulu/* --------------------------------------------- 30*91f16700Schasinglulu * The below macro prints out relevant GIC 31*91f16700Schasinglulu * registers whenever an unhandled exception is 32*91f16700Schasinglulu * taken in BL31. 33*91f16700Schasinglulu * --------------------------------------------- 34*91f16700Schasinglulu */ 35*91f16700Schasinglulu.macro plat_crash_print_regs 36*91f16700Schasinglulu mov_imm x16, PLAT_ARM_GICD_BASE 37*91f16700Schasinglulu mov_imm x17, PLAT_ARM_GICC_BASE 38*91f16700Schasinglulu 39*91f16700Schasinglulu /* Load the gicc reg list to x6 */ 40*91f16700Schasinglulu adr x6, gicc_regs 41*91f16700Schasinglulu /* Load the gicc regs to gp regs used by str_in_crash_buf_print */ 42*91f16700Schasinglulu ldr w8, [x17, #GICC_HPPIR] 43*91f16700Schasinglulu ldr w9, [x17, #GICC_AHPPIR] 44*91f16700Schasinglulu ldr w10, [x17, #GICC_CTLR] 45*91f16700Schasinglulu /* Store to the crash buf and print to cosole */ 46*91f16700Schasinglulu bl str_in_crash_buf_print 47*91f16700Schasinglulu 48*91f16700Schasinglulu /* Print the GICD_ISPENDR regs */ 49*91f16700Schasinglulu add x7, x16, #GICD_ISPENDR 50*91f16700Schasinglulu adr x4, gicd_pend_reg 51*91f16700Schasinglulu bl asm_print_str 52*91f16700Schasinglulu2: 53*91f16700Schasinglulu sub x4, x7, x16 54*91f16700Schasinglulu cmp x4, #0x280 55*91f16700Schasinglulu b.eq 1f 56*91f16700Schasinglulu bl asm_print_hex 57*91f16700Schasinglulu adr x4, spacer 58*91f16700Schasinglulu bl asm_print_str 59*91f16700Schasinglulu ldr x4, [x7], #8 60*91f16700Schasinglulu bl asm_print_hex 61*91f16700Schasinglulu adr x4, newline 62*91f16700Schasinglulu bl asm_print_str 63*91f16700Schasinglulu b 2b 64*91f16700Schasinglulu1: 65*91f16700Schasinglulu adr x6, cci_iface_regs 66*91f16700Schasinglulu /* Store in x7 the base address of the first interface */ 67*91f16700Schasinglulu mov_imm x7, (CCI400_BASE + SLAVE_IFACE_OFFSET( \ 68*91f16700Schasinglulu CCI400_SL_IFACE3_CLUSTER_IX)) 69*91f16700Schasinglulu ldr w8, [x7, #SNOOP_CTRL_REG] 70*91f16700Schasinglulu /* Store in x7 the base address of the second interface */ 71*91f16700Schasinglulu mov_imm x7, (CCI400_BASE + SLAVE_IFACE_OFFSET( \ 72*91f16700Schasinglulu CCI400_SL_IFACE4_CLUSTER_IX)) 73*91f16700Schasinglulu ldr w9, [x7, #SNOOP_CTRL_REG] 74*91f16700Schasinglulu /* Store to the crash buf and print to console */ 75*91f16700Schasinglulu bl str_in_crash_buf_print 76*91f16700Schasinglulu.endm 77*91f16700Schasinglulu 78*91f16700Schasinglulu#endif /* PLAT_MACROS_S */ 79