1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #ifndef HIKEY_LAYOUT_H 8*91f16700Schasinglulu #define HIKEY_LAYOUT_H 9*91f16700Schasinglulu 10*91f16700Schasinglulu /* 11*91f16700Schasinglulu * Platform memory map related constants 12*91f16700Schasinglulu */ 13*91f16700Schasinglulu #define XG2RAM0_BASE 0xF9800000 14*91f16700Schasinglulu #define XG2RAM0_SIZE 0x00400000 15*91f16700Schasinglulu 16*91f16700Schasinglulu /* 17*91f16700Schasinglulu * BL1 is stored in XG2RAM0_HIRQ that is 784KB large (0xF980_0000~0xF98C_4000). 18*91f16700Schasinglulu */ 19*91f16700Schasinglulu #define ONCHIPROM_PARAM_BASE (XG2RAM0_BASE + 0x700) 20*91f16700Schasinglulu #define LOADER_RAM_BASE (XG2RAM0_BASE + 0x800) 21*91f16700Schasinglulu #define BL1_XG2RAM0_OFFSET 0x1000 22*91f16700Schasinglulu 23*91f16700Schasinglulu /* 24*91f16700Schasinglulu * BL1 specific defines. 25*91f16700Schasinglulu * 26*91f16700Schasinglulu * Both loader and BL1_RO region stay in SRAM since they are used to simulate 27*91f16700Schasinglulu * ROM. 28*91f16700Schasinglulu * Loader is used to switch Hi6220 SoC from 32-bit to 64-bit mode. 29*91f16700Schasinglulu * 30*91f16700Schasinglulu * ++++++++++ 0xF980_0000 31*91f16700Schasinglulu * + loader + 32*91f16700Schasinglulu * ++++++++++ 0xF980_1000 33*91f16700Schasinglulu * + BL1_RO + 34*91f16700Schasinglulu * ++++++++++ 0xF981_8000 35*91f16700Schasinglulu * + BL1_RW + 36*91f16700Schasinglulu * ++++++++++ 0xF989_8000 37*91f16700Schasinglulu */ 38*91f16700Schasinglulu #define BL1_RO_BASE (XG2RAM0_BASE + BL1_XG2RAM0_OFFSET) 39*91f16700Schasinglulu #define BL1_RO_LIMIT (XG2RAM0_BASE + 0x18000) 40*91f16700Schasinglulu #define BL1_RW_BASE (BL1_RO_LIMIT) /* 0xf981_8000 */ 41*91f16700Schasinglulu #define BL1_RW_SIZE (0x00080000) 42*91f16700Schasinglulu #define BL1_RW_LIMIT (0xF9898000) 43*91f16700Schasinglulu 44*91f16700Schasinglulu /* 45*91f16700Schasinglulu * Non-Secure BL1U specific defines. 46*91f16700Schasinglulu */ 47*91f16700Schasinglulu #define NS_BL1U_BASE (0xf9828000) 48*91f16700Schasinglulu #define NS_BL1U_SIZE (0x00010000) 49*91f16700Schasinglulu #define NS_BL1U_LIMIT (NS_BL1U_BASE + NS_BL1U_SIZE) 50*91f16700Schasinglulu 51*91f16700Schasinglulu /* 52*91f16700Schasinglulu * BL2 specific defines. 53*91f16700Schasinglulu * 54*91f16700Schasinglulu * Both loader and BL2 region stay in SRAM. 55*91f16700Schasinglulu * Loader is used to switch Hi6220 SoC from 32-bit to 64-bit mode. 56*91f16700Schasinglulu * 57*91f16700Schasinglulu * ++++++++++ 0xF980_0000 58*91f16700Schasinglulu * + loader + 59*91f16700Schasinglulu * ++++++++++ 0xF980_1000 60*91f16700Schasinglulu * + BL2 + 61*91f16700Schasinglulu * ++++++++++ 0xF983_0000 62*91f16700Schasinglulu */ 63*91f16700Schasinglulu #define BL2_BASE (BL1_RO_BASE) /* 0xf980_1000 */ 64*91f16700Schasinglulu #define BL2_LIMIT (0xF9830000) /* 0xf983_0000 */ 65*91f16700Schasinglulu 66*91f16700Schasinglulu /* 67*91f16700Schasinglulu * SCP_BL2 specific defines. 68*91f16700Schasinglulu * In HiKey, SCP_BL2 means MCU firmware. It's loaded into the temporary buffer 69*91f16700Schasinglulu * at 0x0100_0000. Then BL2 will parse the sections and loaded them into 70*91f16700Schasinglulu * predefined separated buffers. 71*91f16700Schasinglulu */ 72*91f16700Schasinglulu #define SCP_BL2_BASE (DDR_BASE + 0x01000000) 73*91f16700Schasinglulu #define SCP_BL2_LIMIT (SCP_BL2_BASE + 0x00100000) 74*91f16700Schasinglulu #define SCP_BL2_SIZE (SCP_BL2_LIMIT - SCP_BL2_BASE) 75*91f16700Schasinglulu 76*91f16700Schasinglulu /* 77*91f16700Schasinglulu * BL31 specific defines. 78*91f16700Schasinglulu */ 79*91f16700Schasinglulu #define BL31_BASE (0xF9858000) /* 0xf985_8000 */ 80*91f16700Schasinglulu #define BL31_LIMIT (0xF9898000) 81*91f16700Schasinglulu 82*91f16700Schasinglulu /* 83*91f16700Schasinglulu * BL3-2 specific defines. 84*91f16700Schasinglulu */ 85*91f16700Schasinglulu 86*91f16700Schasinglulu /* 87*91f16700Schasinglulu * The TSP currently executes from TZC secured area of DRAM or SRAM. 88*91f16700Schasinglulu */ 89*91f16700Schasinglulu #define BL32_SRAM_BASE BL31_LIMIT 90*91f16700Schasinglulu #define BL32_SRAM_LIMIT (BL31_LIMIT+0x80000) /* 512K */ 91*91f16700Schasinglulu 92*91f16700Schasinglulu #define BL32_DRAM_BASE DDR_SEC_BASE 93*91f16700Schasinglulu #define BL32_DRAM_LIMIT (DDR_SEC_BASE+DDR_SEC_SIZE) 94*91f16700Schasinglulu 95*91f16700Schasinglulu #ifdef SPD_opteed 96*91f16700Schasinglulu /* Load pageable part of OP-TEE at end of allocated DRAM space for BL32 */ 97*91f16700Schasinglulu #define HIKEY_OPTEE_PAGEABLE_LOAD_BASE (BL32_DRAM_LIMIT - HIKEY_OPTEE_PAGEABLE_LOAD_SIZE) /* 0x3FC0_0000 */ 98*91f16700Schasinglulu #define HIKEY_OPTEE_PAGEABLE_LOAD_SIZE 0x400000 /* 4MB */ 99*91f16700Schasinglulu #endif 100*91f16700Schasinglulu 101*91f16700Schasinglulu #if (HIKEY_TSP_RAM_LOCATION_ID == HIKEY_DRAM_ID) 102*91f16700Schasinglulu #define TSP_SEC_MEM_BASE BL32_DRAM_BASE 103*91f16700Schasinglulu #define TSP_SEC_MEM_SIZE (BL32_DRAM_LIMIT - BL32_DRAM_BASE) 104*91f16700Schasinglulu #define BL32_BASE BL32_DRAM_BASE 105*91f16700Schasinglulu #define BL32_LIMIT BL32_DRAM_LIMIT 106*91f16700Schasinglulu #elif (HIKEY_TSP_RAM_LOCATION_ID == HIKEY_SRAM_ID) 107*91f16700Schasinglulu #define TSP_SEC_MEM_BASE BL32_SRAM_BASE 108*91f16700Schasinglulu #define TSP_SEC_MEM_SIZE (BL32_SRAM_LIMIT - BL32_SRAM_BASE) 109*91f16700Schasinglulu #define BL32_BASE BL32_SRAM_BASE 110*91f16700Schasinglulu #define BL32_LIMIT BL32_SRAM_LIMIT 111*91f16700Schasinglulu #else 112*91f16700Schasinglulu #error "Currently unsupported HIKEY_TSP_LOCATION_ID value" 113*91f16700Schasinglulu #endif 114*91f16700Schasinglulu 115*91f16700Schasinglulu /* BL32 is mandatory in AArch32 */ 116*91f16700Schasinglulu #ifdef __aarch64__ 117*91f16700Schasinglulu #ifdef SPD_none 118*91f16700Schasinglulu #undef BL32_BASE 119*91f16700Schasinglulu #endif /* SPD_none */ 120*91f16700Schasinglulu #endif 121*91f16700Schasinglulu 122*91f16700Schasinglulu #endif /* HIKEY_LAYOUT_H */ 123