1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #ifndef HI6220_H 8*91f16700Schasinglulu #define HI6220_H 9*91f16700Schasinglulu 10*91f16700Schasinglulu #include <hi6220_regs_acpu.h> 11*91f16700Schasinglulu #include <hi6220_regs_ao.h> 12*91f16700Schasinglulu #include <hi6220_regs_peri.h> 13*91f16700Schasinglulu #include <hi6220_regs_pin.h> 14*91f16700Schasinglulu #include <hi6220_regs_pmctrl.h> 15*91f16700Schasinglulu 16*91f16700Schasinglulu /******************************************************************************* 17*91f16700Schasinglulu * Implementation defined ACTLR_EL2 bit definitions 18*91f16700Schasinglulu ******************************************************************************/ 19*91f16700Schasinglulu #define ACTLR_EL2_L2ACTLR_BIT (1 << 6) 20*91f16700Schasinglulu #define ACTLR_EL2_L2ECTLR_BIT (1 << 5) 21*91f16700Schasinglulu #define ACTLR_EL2_L2CTLR_BIT (1 << 4) 22*91f16700Schasinglulu #define ACTLR_EL2_CPUECTLR_BIT (1 << 1) 23*91f16700Schasinglulu #define ACTLR_EL2_CPUACTLR_BIT (1 << 0) 24*91f16700Schasinglulu 25*91f16700Schasinglulu /******************************************************************************* 26*91f16700Schasinglulu * Implementation defined ACTLR_EL3 bit definitions 27*91f16700Schasinglulu ******************************************************************************/ 28*91f16700Schasinglulu #define ACTLR_EL3_L2ACTLR_BIT (1 << 6) 29*91f16700Schasinglulu #define ACTLR_EL3_L2ECTLR_BIT (1 << 5) 30*91f16700Schasinglulu #define ACTLR_EL3_L2CTLR_BIT (1 << 4) 31*91f16700Schasinglulu #define ACTLR_EL3_CPUECTLR_BIT (1 << 1) 32*91f16700Schasinglulu #define ACTLR_EL3_CPUACTLR_BIT (1 << 0) 33*91f16700Schasinglulu 34*91f16700Schasinglulu /******************************************************************************* 35*91f16700Schasinglulu * CCI-400 related constants 36*91f16700Schasinglulu ******************************************************************************/ 37*91f16700Schasinglulu #define CCI400_BASE 0xF6E90000 38*91f16700Schasinglulu #define CCI400_SL_IFACE3_CLUSTER_IX 3 39*91f16700Schasinglulu #define CCI400_SL_IFACE4_CLUSTER_IX 4 40*91f16700Schasinglulu 41*91f16700Schasinglulu #define DWMMC0_BASE 0xF723D000 42*91f16700Schasinglulu 43*91f16700Schasinglulu #define DWUSB_BASE 0xF72C0000 44*91f16700Schasinglulu 45*91f16700Schasinglulu #define EDMAC_BASE 0xf7370000 46*91f16700Schasinglulu #define EDMAC_SEC_CTRL (EDMAC_BASE + 0x694) 47*91f16700Schasinglulu #define EDMAC_AXI_CONF(x) (EDMAC_BASE + 0x820 + (x << 6)) 48*91f16700Schasinglulu #define EDMAC_SEC_CTRL_INTR_SEC (1 << 1) 49*91f16700Schasinglulu #define EDMAC_SEC_CTRL_GLOBAL_SEC (1 << 0) 50*91f16700Schasinglulu #define EDMAC_CHANNEL_NUMS 16 51*91f16700Schasinglulu 52*91f16700Schasinglulu #define PMUSSI_BASE 0xF8000000 53*91f16700Schasinglulu 54*91f16700Schasinglulu #define SP804_TIMER0_BASE 0xF8008000 55*91f16700Schasinglulu 56*91f16700Schasinglulu #define GPIO0_BASE 0xF8011000 57*91f16700Schasinglulu #define GPIO1_BASE 0xF8012000 58*91f16700Schasinglulu #define GPIO2_BASE 0xF8013000 59*91f16700Schasinglulu #define GPIO3_BASE 0xF8014000 60*91f16700Schasinglulu #define GPIO4_BASE 0xF7020000 61*91f16700Schasinglulu #define GPIO5_BASE 0xF7021000 62*91f16700Schasinglulu #define GPIO6_BASE 0xF7022000 63*91f16700Schasinglulu #define GPIO7_BASE 0xF7023000 64*91f16700Schasinglulu #define GPIO8_BASE 0xF7024000 65*91f16700Schasinglulu #define GPIO9_BASE 0xF7025000 66*91f16700Schasinglulu #define GPIO10_BASE 0xF7026000 67*91f16700Schasinglulu #define GPIO11_BASE 0xF7027000 68*91f16700Schasinglulu #define GPIO12_BASE 0xF7028000 69*91f16700Schasinglulu #define GPIO13_BASE 0xF7029000 70*91f16700Schasinglulu #define GPIO14_BASE 0xF702A000 71*91f16700Schasinglulu #define GPIO15_BASE 0xF702B000 72*91f16700Schasinglulu #define GPIO16_BASE 0xF702C000 73*91f16700Schasinglulu #define GPIO17_BASE 0xF702D000 74*91f16700Schasinglulu #define GPIO18_BASE 0xF702E000 75*91f16700Schasinglulu #define GPIO19_BASE 0xF702F000 76*91f16700Schasinglulu 77*91f16700Schasinglulu #endif /* HI6220_H */ 78