1*91f16700Schasinglulu/* 2*91f16700Schasinglulu * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu#include <arch.h> 8*91f16700Schasinglulu#include <asm_macros.S> 9*91f16700Schasinglulu#include <cortex_a53.h> 10*91f16700Schasinglulu#include <hi6220.h> 11*91f16700Schasinglulu#include <hisi_sram_map.h> 12*91f16700Schasinglulu 13*91f16700Schasinglulu .global pm_asm_code 14*91f16700Schasinglulu .global pm_asm_code_end 15*91f16700Schasinglulu .global v7_asm 16*91f16700Schasinglulu .global v7_asm_end 17*91f16700Schasinglulu 18*91f16700Schasinglulufunc pm_asm_code _align=3 19*91f16700Schasinglulu mov x0, 0 20*91f16700Schasinglulu msr oslar_el1, x0 21*91f16700Schasinglulu 22*91f16700Schasinglulu mrs x0, CORTEX_A53_CPUACTLR_EL1 23*91f16700Schasinglulu bic x0, x0, #(CORTEX_A53_CPUACTLR_EL1_RADIS | \ 24*91f16700Schasinglulu CORTEX_A53_CPUACTLR_EL1_L1RADIS) 25*91f16700Schasinglulu orr x0, x0, #0x180000 26*91f16700Schasinglulu orr x0, x0, #0xe000 27*91f16700Schasinglulu msr CORTEX_A53_CPUACTLR_EL1, x0 28*91f16700Schasinglulu 29*91f16700Schasinglulu mrs x3, actlr_el3 30*91f16700Schasinglulu orr x3, x3, #ACTLR_EL3_L2ECTLR_BIT 31*91f16700Schasinglulu msr actlr_el3, x3 32*91f16700Schasinglulu 33*91f16700Schasinglulu mrs x3, actlr_el2 34*91f16700Schasinglulu orr x3, x3, #ACTLR_EL2_L2ECTLR_BIT 35*91f16700Schasinglulu msr actlr_el2, x3 36*91f16700Schasinglulu 37*91f16700Schasinglulu ldr x3, =PWRCTRL_ACPU_ASM_D_ARM_PARA_AD 38*91f16700Schasinglulu mrs x0, mpidr_el1 39*91f16700Schasinglulu and x1, x0, #MPIDR_CPU_MASK 40*91f16700Schasinglulu and x0, x0, #MPIDR_CLUSTER_MASK 41*91f16700Schasinglulu add x0, x1, x0, LSR #6 42*91f16700Schasinglulupen: ldr x4, [x3, x0, LSL #3] 43*91f16700Schasinglulu cbz x4, pen 44*91f16700Schasinglulu 45*91f16700Schasinglulu mov x0, #0x0 46*91f16700Schasinglulu mov x1, #0x0 47*91f16700Schasinglulu mov x2, #0x0 48*91f16700Schasinglulu mov x3, #0x0 49*91f16700Schasinglulu br x4 50*91f16700Schasinglulu 51*91f16700Schasinglulu .ltorg 52*91f16700Schasinglulu 53*91f16700Schasinglulupm_asm_code_end: 54*91f16700Schasingluluendfunc pm_asm_code 55*91f16700Schasinglulu 56*91f16700Schasinglulu /* 57*91f16700Schasinglulu * By default, all cores in Hi6220 reset with aarch32 mode. 58*91f16700Schasinglulu * Now hardcode ARMv7 instructions to execute warm reset for 59*91f16700Schasinglulu * switching aarch64 mode. 60*91f16700Schasinglulu */ 61*91f16700Schasinglulu .align 3 62*91f16700Schasinglulu .section .rodata.v7_asm, "aS" 63*91f16700Schasingluluv7_asm: 64*91f16700Schasinglulu .word 0xE1A00000 // nop 65*91f16700Schasinglulu .word 0xE3A02003 // mov r2, #3 66*91f16700Schasinglulu .word 0xEE0C2F50 // mcr 15, 0, r2, cr12, cr0, {2} 67*91f16700Schasinglulu .word 0xE320F003 // wfi 68*91f16700Schasinglulu 69*91f16700Schasinglulu .ltorg 70*91f16700Schasingluluv7_asm_end: 71