1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #include <stdarg.h> 8*91f16700Schasinglulu #include <stdio.h> 9*91f16700Schasinglulu #include <string.h> 10*91f16700Schasinglulu 11*91f16700Schasinglulu #include <platform_def.h> 12*91f16700Schasinglulu 13*91f16700Schasinglulu #include <common/debug.h> 14*91f16700Schasinglulu #include <lib/mmio.h> 15*91f16700Schasinglulu 16*91f16700Schasinglulu #include <hi6220_regs_acpu.h> 17*91f16700Schasinglulu #include <hi6220_regs_ao.h> 18*91f16700Schasinglulu #include <hisi_ipc.h> 19*91f16700Schasinglulu #include <hisi_pwrc.h> 20*91f16700Schasinglulu #include <hisi_sram_map.h> 21*91f16700Schasinglulu 22*91f16700Schasinglulu #define CLUSTER_CORE_COUNT (4) 23*91f16700Schasinglulu #define CLUSTER_CORE_MASK ((1 << CLUSTER_CORE_COUNT) - 1) 24*91f16700Schasinglulu 25*91f16700Schasinglulu void hisi_pwrc_set_core_bx_addr(unsigned int core, unsigned int cluster, 26*91f16700Schasinglulu uintptr_t entry_point) 27*91f16700Schasinglulu { 28*91f16700Schasinglulu uintptr_t *core_entry = (uintptr_t *)PWRCTRL_ACPU_ASM_D_ARM_PARA_AD; 29*91f16700Schasinglulu unsigned int i; 30*91f16700Schasinglulu 31*91f16700Schasinglulu if (!core_entry) { 32*91f16700Schasinglulu INFO("%s: core entry point is null!\n", __func__); 33*91f16700Schasinglulu return; 34*91f16700Schasinglulu } 35*91f16700Schasinglulu 36*91f16700Schasinglulu i = cluster * CLUSTER_CORE_COUNT + core; 37*91f16700Schasinglulu mmio_write_64((uintptr_t)(core_entry + i), entry_point); 38*91f16700Schasinglulu } 39*91f16700Schasinglulu 40*91f16700Schasinglulu void hisi_pwrc_set_cluster_wfi(unsigned int cluster) 41*91f16700Schasinglulu { 42*91f16700Schasinglulu unsigned int reg = 0; 43*91f16700Schasinglulu 44*91f16700Schasinglulu if (cluster == 0) { 45*91f16700Schasinglulu reg = mmio_read_32(ACPU_SC_SNOOP_PWD); 46*91f16700Schasinglulu reg |= PD_DETECT_START0; 47*91f16700Schasinglulu mmio_write_32(ACPU_SC_SNOOP_PWD, reg); 48*91f16700Schasinglulu } else if (cluster == 1) { 49*91f16700Schasinglulu reg = mmio_read_32(ACPU_SC_SNOOP_PWD); 50*91f16700Schasinglulu reg |= PD_DETECT_START1; 51*91f16700Schasinglulu mmio_write_32(ACPU_SC_SNOOP_PWD, reg); 52*91f16700Schasinglulu } 53*91f16700Schasinglulu } 54*91f16700Schasinglulu 55*91f16700Schasinglulu void hisi_pwrc_enable_debug(unsigned int core, unsigned int cluster) 56*91f16700Schasinglulu { 57*91f16700Schasinglulu unsigned int val, enable; 58*91f16700Schasinglulu 59*91f16700Schasinglulu enable = 1U << (core + PDBGUP_CLUSTER1_SHIFT * cluster); 60*91f16700Schasinglulu 61*91f16700Schasinglulu /* Enable debug module */ 62*91f16700Schasinglulu val = mmio_read_32(ACPU_SC_PDBGUP_MBIST); 63*91f16700Schasinglulu mmio_write_32(ACPU_SC_PDBGUP_MBIST, val | enable); 64*91f16700Schasinglulu do { 65*91f16700Schasinglulu /* RAW barrier */ 66*91f16700Schasinglulu val = mmio_read_32(ACPU_SC_PDBGUP_MBIST); 67*91f16700Schasinglulu } while (!(val & enable)); 68*91f16700Schasinglulu } 69*91f16700Schasinglulu 70*91f16700Schasinglulu int hisi_pwrc_setup(void) 71*91f16700Schasinglulu { 72*91f16700Schasinglulu unsigned int reg, sec_entrypoint; 73*91f16700Schasinglulu extern char pm_asm_code[], pm_asm_code_end[]; 74*91f16700Schasinglulu extern char v7_asm[], v7_asm_end[]; 75*91f16700Schasinglulu 76*91f16700Schasinglulu sec_entrypoint = PWRCTRL_ACPU_ASM_CODE_BASE; 77*91f16700Schasinglulu mmio_write_32(ACPU_SC_CPUx_RVBARADDR(0), sec_entrypoint >> 2); 78*91f16700Schasinglulu mmio_write_32(ACPU_SC_CPUx_RVBARADDR(1), sec_entrypoint >> 2); 79*91f16700Schasinglulu mmio_write_32(ACPU_SC_CPUx_RVBARADDR(2), sec_entrypoint >> 2); 80*91f16700Schasinglulu mmio_write_32(ACPU_SC_CPUx_RVBARADDR(3), sec_entrypoint >> 2); 81*91f16700Schasinglulu mmio_write_32(ACPU_SC_CPUx_RVBARADDR(4), sec_entrypoint >> 2); 82*91f16700Schasinglulu mmio_write_32(ACPU_SC_CPUx_RVBARADDR(5), sec_entrypoint >> 2); 83*91f16700Schasinglulu mmio_write_32(ACPU_SC_CPUx_RVBARADDR(6), sec_entrypoint >> 2); 84*91f16700Schasinglulu mmio_write_32(ACPU_SC_CPUx_RVBARADDR(7), sec_entrypoint >> 2); 85*91f16700Schasinglulu 86*91f16700Schasinglulu memset((void *)PWRCTRL_ACPU_ASM_SPACE_ADDR, 0, 0x400); 87*91f16700Schasinglulu memcpy((void *)PWRCTRL_ACPU_ASM_SPACE_ADDR, (void *)v7_asm, 88*91f16700Schasinglulu v7_asm_end - v7_asm); 89*91f16700Schasinglulu 90*91f16700Schasinglulu memcpy((void *)PWRCTRL_ACPU_ASM_CODE_BASE, (void *)pm_asm_code, 91*91f16700Schasinglulu pm_asm_code_end - pm_asm_code); 92*91f16700Schasinglulu 93*91f16700Schasinglulu reg = mmio_read_32(AO_SC_SYS_CTRL1); 94*91f16700Schasinglulu /* Remap SRAM address for ACPU */ 95*91f16700Schasinglulu reg |= AO_SC_SYS_CTRL1_REMAP_SRAM_AARM | 96*91f16700Schasinglulu AO_SC_SYS_CTRL1_REMAP_SRAM_AARM_MSK; 97*91f16700Schasinglulu 98*91f16700Schasinglulu /* Enable reset signal for watchdog */ 99*91f16700Schasinglulu reg |= AO_SC_SYS_CTRL1_AARM_WD_RST_CFG | 100*91f16700Schasinglulu AO_SC_SYS_CTRL1_AARM_WD_RST_CFG_MSK; 101*91f16700Schasinglulu mmio_write_32(AO_SC_SYS_CTRL1, reg); 102*91f16700Schasinglulu 103*91f16700Schasinglulu return 0; 104*91f16700Schasinglulu } 105