1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #include <assert.h> 8*91f16700Schasinglulu 9*91f16700Schasinglulu #include <arch_helpers.h> 10*91f16700Schasinglulu #include <common/bl_common.h> 11*91f16700Schasinglulu #include <common/debug.h> 12*91f16700Schasinglulu #include <lib/mmio.h> 13*91f16700Schasinglulu #include <lib/xlat_tables/xlat_tables.h> 14*91f16700Schasinglulu #include <plat/common/platform.h> 15*91f16700Schasinglulu 16*91f16700Schasinglulu #include <hikey_def.h> 17*91f16700Schasinglulu #include <hikey_layout.h> 18*91f16700Schasinglulu 19*91f16700Schasinglulu #define MAP_DDR MAP_REGION_FLAT(DDR_BASE, \ 20*91f16700Schasinglulu DDR_SIZE - DDR_SEC_SIZE, \ 21*91f16700Schasinglulu MT_DEVICE | MT_RW | MT_NS) 22*91f16700Schasinglulu 23*91f16700Schasinglulu #define MAP_DEVICE MAP_REGION_FLAT(DEVICE_BASE, \ 24*91f16700Schasinglulu DEVICE_SIZE, \ 25*91f16700Schasinglulu MT_DEVICE | MT_RW | MT_SECURE) 26*91f16700Schasinglulu 27*91f16700Schasinglulu #define MAP_TSP_MEM MAP_REGION_FLAT(TSP_SEC_MEM_BASE, \ 28*91f16700Schasinglulu TSP_SEC_MEM_SIZE, \ 29*91f16700Schasinglulu MT_MEMORY | MT_RW | MT_SECURE) 30*91f16700Schasinglulu 31*91f16700Schasinglulu #define MAP_ROM_PARAM MAP_REGION_FLAT(XG2RAM0_BASE, \ 32*91f16700Schasinglulu BL1_XG2RAM0_OFFSET, \ 33*91f16700Schasinglulu MT_DEVICE | MT_RO | MT_SECURE) 34*91f16700Schasinglulu 35*91f16700Schasinglulu #define MAP_SRAM MAP_REGION_FLAT(SRAM_BASE, \ 36*91f16700Schasinglulu SRAM_SIZE, \ 37*91f16700Schasinglulu MT_DEVICE | MT_RW | MT_SECURE) 38*91f16700Schasinglulu 39*91f16700Schasinglulu /* 40*91f16700Schasinglulu * BL1 needs to access the areas of MMC_SRAM. 41*91f16700Schasinglulu * BL1 loads BL2 from eMMC into SRAM before DDR initialized. 42*91f16700Schasinglulu */ 43*91f16700Schasinglulu #define MAP_MMC_SRAM MAP_REGION_FLAT(HIKEY_BL1_MMC_DESC_BASE, \ 44*91f16700Schasinglulu HIKEY_BL1_MMC_DESC_SIZE + \ 45*91f16700Schasinglulu HIKEY_BL1_MMC_DATA_SIZE, \ 46*91f16700Schasinglulu MT_DEVICE | MT_RW | MT_SECURE) 47*91f16700Schasinglulu 48*91f16700Schasinglulu /* 49*91f16700Schasinglulu * Table of regions for different BL stages to map using the MMU. 50*91f16700Schasinglulu * This doesn't include Trusted RAM as the 'mem_layout' argument passed to 51*91f16700Schasinglulu * hikey_init_mmu_elx() will give the available subset of that, 52*91f16700Schasinglulu */ 53*91f16700Schasinglulu #ifdef IMAGE_BL1 54*91f16700Schasinglulu static const mmap_region_t hikey_mmap[] = { 55*91f16700Schasinglulu MAP_DEVICE, 56*91f16700Schasinglulu MAP_ROM_PARAM, 57*91f16700Schasinglulu MAP_MMC_SRAM, 58*91f16700Schasinglulu {0} 59*91f16700Schasinglulu }; 60*91f16700Schasinglulu #endif 61*91f16700Schasinglulu 62*91f16700Schasinglulu #ifdef IMAGE_BL2 63*91f16700Schasinglulu static const mmap_region_t hikey_mmap[] = { 64*91f16700Schasinglulu MAP_DDR, 65*91f16700Schasinglulu MAP_DEVICE, 66*91f16700Schasinglulu MAP_TSP_MEM, 67*91f16700Schasinglulu MAP_SRAM, 68*91f16700Schasinglulu {0} 69*91f16700Schasinglulu }; 70*91f16700Schasinglulu #endif 71*91f16700Schasinglulu 72*91f16700Schasinglulu #ifdef IMAGE_BL31 73*91f16700Schasinglulu static const mmap_region_t hikey_mmap[] = { 74*91f16700Schasinglulu MAP_DEVICE, 75*91f16700Schasinglulu MAP_SRAM, 76*91f16700Schasinglulu MAP_TSP_MEM, 77*91f16700Schasinglulu {0} 78*91f16700Schasinglulu }; 79*91f16700Schasinglulu #endif 80*91f16700Schasinglulu 81*91f16700Schasinglulu #ifdef IMAGE_BL32 82*91f16700Schasinglulu static const mmap_region_t hikey_mmap[] = { 83*91f16700Schasinglulu MAP_DEVICE, 84*91f16700Schasinglulu MAP_DDR, 85*91f16700Schasinglulu {0} 86*91f16700Schasinglulu }; 87*91f16700Schasinglulu #endif 88*91f16700Schasinglulu 89*91f16700Schasinglulu /* 90*91f16700Schasinglulu * Macro generating the code for the function setting up the pagetables as per 91*91f16700Schasinglulu * the platform memory map & initialize the mmu, for the given exception level 92*91f16700Schasinglulu */ 93*91f16700Schasinglulu #define HIKEY_CONFIGURE_MMU_EL(_el) \ 94*91f16700Schasinglulu void hikey_init_mmu_el##_el(unsigned long total_base, \ 95*91f16700Schasinglulu unsigned long total_size, \ 96*91f16700Schasinglulu unsigned long ro_start, \ 97*91f16700Schasinglulu unsigned long ro_limit, \ 98*91f16700Schasinglulu unsigned long coh_start, \ 99*91f16700Schasinglulu unsigned long coh_limit) \ 100*91f16700Schasinglulu { \ 101*91f16700Schasinglulu mmap_add_region(total_base, total_base, \ 102*91f16700Schasinglulu total_size, \ 103*91f16700Schasinglulu MT_MEMORY | MT_RW | MT_SECURE); \ 104*91f16700Schasinglulu mmap_add_region(ro_start, ro_start, \ 105*91f16700Schasinglulu ro_limit - ro_start, \ 106*91f16700Schasinglulu MT_MEMORY | MT_RO | MT_SECURE); \ 107*91f16700Schasinglulu mmap_add_region(coh_start, coh_start, \ 108*91f16700Schasinglulu coh_limit - coh_start, \ 109*91f16700Schasinglulu MT_DEVICE | MT_RW | MT_SECURE); \ 110*91f16700Schasinglulu mmap_add(hikey_mmap); \ 111*91f16700Schasinglulu init_xlat_tables(); \ 112*91f16700Schasinglulu \ 113*91f16700Schasinglulu enable_mmu_el##_el(0); \ 114*91f16700Schasinglulu } 115*91f16700Schasinglulu 116*91f16700Schasinglulu /* Define EL1 and EL3 variants of the function initialising the MMU */ 117*91f16700Schasinglulu HIKEY_CONFIGURE_MMU_EL(1) 118*91f16700Schasinglulu HIKEY_CONFIGURE_MMU_EL(3) 119*91f16700Schasinglulu 120*91f16700Schasinglulu unsigned long plat_get_ns_image_entrypoint(void) 121*91f16700Schasinglulu { 122*91f16700Schasinglulu return HIKEY_NS_IMAGE_OFFSET; 123*91f16700Schasinglulu } 124*91f16700Schasinglulu 125*91f16700Schasinglulu unsigned int plat_get_syscnt_freq2(void) 126*91f16700Schasinglulu { 127*91f16700Schasinglulu return 1200000; 128*91f16700Schasinglulu } 129