1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2019-2020, ARM Limited and Contributors. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #include <arch.h> 8*91f16700Schasinglulu #include <arch_helpers.h> 9*91f16700Schasinglulu #include <drivers/arm/ccn.h> 10*91f16700Schasinglulu 11*91f16700Schasinglulu #include <platform_def.h> 12*91f16700Schasinglulu 13*91f16700Schasinglulu static const unsigned char master_to_rn_id_map[] = { 14*91f16700Schasinglulu PLAT_BRCM_CLUSTER_TO_CCN_ID_MAP 15*91f16700Schasinglulu }; 16*91f16700Schasinglulu 17*91f16700Schasinglulu static const ccn_desc_t bcm_ccn_desc = { 18*91f16700Schasinglulu .periphbase = PLAT_BRCM_CCN_BASE, 19*91f16700Schasinglulu .num_masters = ARRAY_SIZE(master_to_rn_id_map), 20*91f16700Schasinglulu .master_to_rn_id_map = master_to_rn_id_map 21*91f16700Schasinglulu }; 22*91f16700Schasinglulu 23*91f16700Schasinglulu void plat_brcm_interconnect_init(void) 24*91f16700Schasinglulu { 25*91f16700Schasinglulu ccn_init(&bcm_ccn_desc); 26*91f16700Schasinglulu } 27*91f16700Schasinglulu 28*91f16700Schasinglulu void plat_brcm_interconnect_enter_coherency(void) 29*91f16700Schasinglulu { 30*91f16700Schasinglulu ccn_enter_snoop_dvm_domain(1 << MPIDR_AFFLVL1_VAL(read_mpidr_el1())); 31*91f16700Schasinglulu } 32*91f16700Schasinglulu 33*91f16700Schasinglulu void plat_brcm_interconnect_exit_coherency(void) 34*91f16700Schasinglulu { 35*91f16700Schasinglulu ccn_exit_snoop_dvm_domain(1 << MPIDR_AFFLVL1_VAL(read_mpidr_el1())); 36*91f16700Schasinglulu } 37