1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2016 - 2020, Broadcom 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #ifndef PAXB_H 8*91f16700Schasinglulu #define PAXB_H 9*91f16700Schasinglulu 10*91f16700Schasinglulu /* total number of PCIe cores */ 11*91f16700Schasinglulu #define NUM_OF_SR_PCIE_CORES 8 12*91f16700Schasinglulu #define NUM_OF_NS3Z_PCIE_CORES 1 13*91f16700Schasinglulu 14*91f16700Schasinglulu /* 15*91f16700Schasinglulu * List of PCIe core and PAXB wrapper memory power registers 16*91f16700Schasinglulu */ 17*91f16700Schasinglulu #define PCIE_CORE_BASE 0x40000800 18*91f16700Schasinglulu #define PCIE_CORE_SOFT_RST_CFG_BASE (PCIE_CORE_BASE + 0x40) 19*91f16700Schasinglulu #define PCIE_CORE_SOFT_RST 0x1 20*91f16700Schasinglulu #define PCIE_CORE_ISO_CFG_BASE (PCIE_CORE_BASE + 0x54) 21*91f16700Schasinglulu #define PCIE_CORE_MEM_ISO 0x2 22*91f16700Schasinglulu #define PCIE_CORE_ISO 0x1 23*91f16700Schasinglulu 24*91f16700Schasinglulu #define PCIE_CORE_MEM_PWR_BASE (PCIE_CORE_BASE + 0x58) 25*91f16700Schasinglulu #define PCIE_PAXB_MEM_PWR_BASE (PCIE_CORE_BASE + 0x5c) 26*91f16700Schasinglulu #define PCIE_CORE_PMI_CFG_BASE (PCIE_CORE_BASE + 0x64) 27*91f16700Schasinglulu #define PCIE_CORE_RESERVED_CFG (PCIE_CORE_BASE + 0x6c) 28*91f16700Schasinglulu #define PCIE_CORE_MEM_PWR_STATUS_BASE (PCIE_CORE_BASE + 0x74) 29*91f16700Schasinglulu #define PCIE_PAXB_MEM_PWR_STATUS_BASE (PCIE_CORE_BASE + 0x78) 30*91f16700Schasinglulu #define PCIE_CORE_PWR_OFFSET 0x100 31*91f16700Schasinglulu 32*91f16700Schasinglulu #define SR_A0_DEVICE_ID 0xd713 33*91f16700Schasinglulu #define SR_B0_DEVICE_ID 0xd714 34*91f16700Schasinglulu /* TODO: Modify device ID once available */ 35*91f16700Schasinglulu #define NS3Z_DEVICE_ID 0xd715 36*91f16700Schasinglulu 37*91f16700Schasinglulu /* FIXME: change link speed to GEN3 when it's ready */ 38*91f16700Schasinglulu #define GEN1_LINK_SPEED 1 39*91f16700Schasinglulu #define GEN2_LINK_SPEED 2 40*91f16700Schasinglulu #define GEN3_LINK_SPEED 3 41*91f16700Schasinglulu 42*91f16700Schasinglulu typedef struct { 43*91f16700Schasinglulu uint32_t type; 44*91f16700Schasinglulu uint32_t device_id; 45*91f16700Schasinglulu uint32_t pipemux_idx; 46*91f16700Schasinglulu uint32_t num_cores; 47*91f16700Schasinglulu int (*pipemux_init)(void); 48*91f16700Schasinglulu int (*phy_init)(void); 49*91f16700Schasinglulu int (*core_needs_enable)(unsigned int core_idx); 50*91f16700Schasinglulu unsigned int (*get_link_width)(unsigned int core_idx); 51*91f16700Schasinglulu unsigned int (*get_link_speed)(void); 52*91f16700Schasinglulu } paxb_cfg; 53*91f16700Schasinglulu 54*91f16700Schasinglulu enum paxb_type { 55*91f16700Schasinglulu PAXB_SR, 56*91f16700Schasinglulu PAXB_NS3Z, 57*91f16700Schasinglulu }; 58*91f16700Schasinglulu 59*91f16700Schasinglulu extern const paxb_cfg *paxb; 60*91f16700Schasinglulu 61*91f16700Schasinglulu #ifdef USE_PAXB 62*91f16700Schasinglulu void paxb_init(void); 63*91f16700Schasinglulu void paxb_rc_cfg_write(unsigned int core_idx, unsigned int where, 64*91f16700Schasinglulu uint32_t val); 65*91f16700Schasinglulu unsigned int paxb_rc_cfg_read(unsigned int core_idx, unsigned int where); 66*91f16700Schasinglulu int pcie_core_needs_enable(unsigned int core_idx); 67*91f16700Schasinglulu const paxb_cfg *paxb_get_sr_config(void); 68*91f16700Schasinglulu #else 69*91f16700Schasinglulu static inline void paxb_init(void) 70*91f16700Schasinglulu { 71*91f16700Schasinglulu } 72*91f16700Schasinglulu #endif 73*91f16700Schasinglulu 74*91f16700Schasinglulu #endif /* PAXB_H */ 75