1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2015 - 2020, Broadcom 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #include <arch_helpers.h> 8*91f16700Schasinglulu #include <common/debug.h> 9*91f16700Schasinglulu #include <lib/mmio.h> 10*91f16700Schasinglulu 11*91f16700Schasinglulu #include <platform_def.h> 12*91f16700Schasinglulu #include <timer_sync.h> 13*91f16700Schasinglulu 14*91f16700Schasinglulu /******************************************************************************* 15*91f16700Schasinglulu * Defines related to time sync and satelite timers 16*91f16700Schasinglulu ******************************************************************************/ 17*91f16700Schasinglulu #define TIME_SYNC_WR_ENA ((uint32_t)0xACCE55 << 8) 18*91f16700Schasinglulu #define IHOST_STA_TMR_CTRL 0x1800 19*91f16700Schasinglulu #define IHOST_SAT_TMR_INC_L 0x1814 20*91f16700Schasinglulu #define IHOST_SAT_TMR_INC_H 0x1818 21*91f16700Schasinglulu 22*91f16700Schasinglulu #define SAT_TMR_CYCLE_DELAY 2 23*91f16700Schasinglulu #define SAT_TMR_32BIT_WRAP_VAL (BIT_64(32) - SAT_TMR_CYCLE_DELAY) 24*91f16700Schasinglulu 25*91f16700Schasinglulu void ihost_enable_satellite_timer(unsigned int cluster_id) 26*91f16700Schasinglulu { 27*91f16700Schasinglulu uintptr_t ihost_base; 28*91f16700Schasinglulu uint32_t time_lx, time_h; 29*91f16700Schasinglulu uintptr_t ihost_enable; 30*91f16700Schasinglulu 31*91f16700Schasinglulu VERBOSE("Program iHost%u satellite timer\n", cluster_id); 32*91f16700Schasinglulu ihost_base = IHOST0_BASE + cluster_id * IHOST_ADDR_SPACE; 33*91f16700Schasinglulu 34*91f16700Schasinglulu /* this read starts the satellite timer counting from 0 */ 35*91f16700Schasinglulu ihost_enable = CENTRAL_TIMER_GET_IHOST_ENA_BASE + cluster_id * 4; 36*91f16700Schasinglulu time_lx = mmio_read_32(ihost_enable); 37*91f16700Schasinglulu 38*91f16700Schasinglulu /* 39*91f16700Schasinglulu * Increment the satellite timer by the central timer plus 2 40*91f16700Schasinglulu * to accommodate for a 1 cycle delay through NOC 41*91f16700Schasinglulu * plus counter starting from 0. 42*91f16700Schasinglulu */ 43*91f16700Schasinglulu mmio_write_32(ihost_base + IHOST_SAT_TMR_INC_L, 44*91f16700Schasinglulu time_lx + SAT_TMR_CYCLE_DELAY); 45*91f16700Schasinglulu 46*91f16700Schasinglulu /* 47*91f16700Schasinglulu * Read the latched upper data, if lx will wrap by adding 2 to it 48*91f16700Schasinglulu * we need to handle the wrap 49*91f16700Schasinglulu */ 50*91f16700Schasinglulu time_h = mmio_read_32(CENTRAL_TIMER_GET_H); 51*91f16700Schasinglulu if (time_lx >= SAT_TMR_32BIT_WRAP_VAL) 52*91f16700Schasinglulu mmio_write_32(ihost_base + IHOST_SAT_TMR_INC_H, time_h + 1); 53*91f16700Schasinglulu else 54*91f16700Schasinglulu mmio_write_32(ihost_base + IHOST_SAT_TMR_INC_H, time_h); 55*91f16700Schasinglulu } 56*91f16700Schasinglulu 57*91f16700Schasinglulu void brcm_timer_sync_init(void) 58*91f16700Schasinglulu { 59*91f16700Schasinglulu unsigned int cluster_id; 60*91f16700Schasinglulu 61*91f16700Schasinglulu /* Get the Time Sync module out of reset */ 62*91f16700Schasinglulu mmio_setbits_32(CDRU_MISC_RESET_CONTROL, 63*91f16700Schasinglulu BIT(CDRU_MISC_RESET_CONTROL_TS_RESET_N)); 64*91f16700Schasinglulu 65*91f16700Schasinglulu /* Deassert the Central Timer TIMER_EN signal for all module */ 66*91f16700Schasinglulu mmio_write_32(CENTRAL_TIMER_SAT_TMR_ENA, TIME_SYNC_WR_ENA); 67*91f16700Schasinglulu 68*91f16700Schasinglulu /* enables/programs iHost0 satellite timer*/ 69*91f16700Schasinglulu cluster_id = MPIDR_AFFLVL1_VAL(read_mpidr()); 70*91f16700Schasinglulu ihost_enable_satellite_timer(cluster_id); 71*91f16700Schasinglulu } 72