1*91f16700Schasinglulu/* SPDX-License-Identifier: BSD-3-Clause */ 2*91f16700Schasinglulu/* 3*91f16700Schasinglulu * Copyright (C) 2024, Charleye <wangkart@aliyun.com> 4*91f16700Schasinglulu * All rights reserved. 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu#include <arch.h> 8*91f16700Schasinglulu#include <asm_macros.S> 9*91f16700Schasinglulu#include <assert_macros.S> 10*91f16700Schasinglulu#include <platform_def.h> 11*91f16700Schasinglulu 12*91f16700Schasinglulu .global lmt_calc_core_pos 13*91f16700Schasinglulu .global plat_my_core_pos 14*91f16700Schasinglulu .global platform_mem_init 15*91f16700Schasinglulu .global plat_is_my_cpu_primary 16*91f16700Schasinglulu .global plat_secondary_cold_boot_setup 17*91f16700Schasinglulu .globl plat_get_my_entrypoint 18*91f16700Schasinglulu 19*91f16700Schasinglulu/* 20*91f16700Schasinglulu * unsigned int lmt_calc_core_pos(u_register_t mpidr) 21*91f16700Schasinglulu * core_pos = (cluster_id * max_cpus_per_cluster) + core_id 22*91f16700Schasinglulu */ 23*91f16700Schasinglulufunc lmt_calc_core_pos 24*91f16700Schasinglulu and x1, x0, #MPIDR_CPU_MASK 25*91f16700Schasinglulu and x0, x0, #MPIDR_CLUSTER_MASK 26*91f16700Schasinglulu add x0, x1, x0, lsr #6 27*91f16700Schasinglulu ret 28*91f16700Schasingluluendfunc lmt_calc_core_pos 29*91f16700Schasinglulu 30*91f16700Schasinglulufunc plat_my_core_pos 31*91f16700Schasinglulu mrs x0, mpidr_el1 32*91f16700Schasinglulu lsr x0, x0, #8 33*91f16700Schasinglulu b lmt_calc_core_pos 34*91f16700Schasingluluendfunc plat_my_core_pos 35*91f16700Schasinglulu 36*91f16700Schasinglulufunc platform_mem_init 37*91f16700Schasinglulu ret 38*91f16700Schasingluluendfunc platform_mem_init 39*91f16700Schasinglulu 40*91f16700Schasinglulu/* 41*91f16700Schasinglulu * Secondary CPUs are placed in a holding pen, waiting for their mailbox 42*91f16700Schasinglulu * to be populated. Note that all CPUs share the same mailbox ; therefore, 43*91f16700Schasinglulu * populating it will release all CPUs from their holding pen. If 44*91f16700Schasinglulu * finer-grained control is needed then this should be handled in the 45*91f16700Schasinglulu * code that secondary CPUs jump to. 46*91f16700Schasinglulu */ 47*91f16700Schasinglulufunc plat_secondary_cold_boot_setup 48*91f16700Schasinglulu /* Calculate address of our hold entry */ 49*91f16700Schasinglulu bl plat_my_core_pos 50*91f16700Schasinglulu lsl x0, x0, #PLAT_LMT_HOLD_ENTRY_SHIFT 51*91f16700Schasinglulu mov_imm x2, PLAT_LMT_HOLD_BASE 52*91f16700Schasinglulu 53*91f16700Schasinglulu /* Wait until we have a go */ 54*91f16700Schasinglulupoll_mailbox: 55*91f16700Schasinglulu ldr x1, [x2, x0] 56*91f16700Schasinglulu cbz x1, 1f 57*91f16700Schasinglulu 58*91f16700Schasinglulu /* Clear the mailbox again ready for next time. */ 59*91f16700Schasinglulu mov x1, #PLAT_LMT_HOLD_STATE_WAIT 60*91f16700Schasinglulu str x1, [x2, x0] 61*91f16700Schasinglulu 62*91f16700Schasinglulu /* Jump to the provided entrypoint. */ 63*91f16700Schasinglulu mov_imm x0, PLAT_LMT_TRUSTED_MAILBOX_BASE 64*91f16700Schasinglulu ldr x1, [x0] 65*91f16700Schasinglulu br x1 66*91f16700Schasinglulu1: 67*91f16700Schasinglulu wfe 68*91f16700Schasinglulu b poll_mailbox 69*91f16700Schasingluluendfunc plat_secondary_cold_boot_setup 70*91f16700Schasinglulu 71*91f16700Schasinglulufunc plat_get_my_entrypoint 72*91f16700Schasinglulu /* TODO support warm boot */ 73*91f16700Schasinglulu mov x0, #0 74*91f16700Schasinglulu ret 75*91f16700Schasingluluendfunc plat_get_my_entrypoint 76*91f16700Schasinglulu 77*91f16700Schasinglulu/* 78*91f16700Schasinglulu * Find out whether the current cpu is the primary 79*91f16700Schasinglulu * cpu (applicable only after a cold boot) 80*91f16700Schasinglulu */ 81*91f16700Schasinglulufunc plat_is_my_cpu_primary 82*91f16700Schasinglulu mrs x0, mpidr_el1 83*91f16700Schasinglulu and x0, x0, #(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK) 84*91f16700Schasinglulu cmp x0, #PLAT_LMT_PRIMARY_CPU 85*91f16700Schasinglulu cset w0, eq 86*91f16700Schasinglulu ret 87*91f16700Schasingluluendfunc plat_is_my_cpu_primary 88