1 /* SPDX-License-Identifier: BSD-3-Clause */ 2 /* 3 * Copyright (C) 2024, Charleye <wangkart@aliyun.com> 4 * All rights reserved. 5 */ 6 7 #ifndef PLATFORM_DEF_H 8 #define PLATFORM_DEF_H 9 10 #include <lib/utils_def.h> 11 #include <plat/common/common_def.h> 12 13 /* CPU topology */ 14 #define PLAT_MAX_CORES_PER_CLUSTER U(4) 15 #define PLAT_CLUSTER_COUNT U(2) 16 #define PLATFORM_CORE_COUNT (PLAT_CLUSTER_COUNT * PLAT_MAX_CORES_PER_CLUSTER) 17 18 #define PLAT_MAX_PWR_LVL U(1) 19 #define PLAT_MAX_RET_STATE U(1) 20 #define PLAT_MAX_OFF_STATE U(2) 21 22 /* Local power state for power domains in Run state. */ 23 #define LMT_LOCAL_STATE_RUN U(0) 24 /* Local power state for retention. Valid only for CPU power domains */ 25 #define LMT_LOCAL_STATE_RET U(1) 26 /* 27 * Local power state for OFF/power-down. Valid for CPU and cluster power 28 * domains. 29 */ 30 #define LMT_LOCAL_STATE_OFF U(2) 31 32 /* 33 * Macros used to parse state information from State-ID if it is using the 34 * recommended encoding for State-ID. 35 */ 36 #define LMT_LOCAL_PSTATE_WIDTH U(4) 37 #define LMT_LOCAL_PSTATE_MASK ((1 << LMT_LOCAL_PSTATE_WIDTH) - 1) 38 39 #define CACHE_WRITEBACK_SHIFT U(6) 40 #define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) 41 42 /* xlat table v2 related to contants */ 43 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 40) 44 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 40) 45 #define MAX_XLAT_TABLES U(8) 46 #define MAX_MMAP_REGIONS U(8) 47 48 #define PLATFORM_STACK_SIZE (1UL << 12) 49 50 /* physical memory related constants */ 51 #define LMT_DRAM_BASE ULL(0x400000000) 52 #define LMT_NS_DDR_SIZE (ULL(0x10) * SZ_1G) 53 #define LMT_BL31_IMG_OFFSET 0x00104000 54 #define LMT_BL32_IMG_OFFSET 0x04000000 55 #define LMT_BL33_IMG_OFFSET 0x00200000 56 57 #define LMT_IRAM_BASE 0x00000000 58 #define LMT_IRAM_SIZE SZ_128K 59 60 #define SHARED_RAM_BASE (LMT_IRAM_BASE + LMT_IRAM_SIZE - SZ_4K) 61 #define SHARED_RAM_SIZE SZ_4K 62 63 #define PLAT_LMT_TRUSTED_MAILBOX_BASE SHARED_RAM_BASE 64 #define PLAT_LMT_TRUSTED_MAILBOX_SIZE (8 + PLAT_LMT_HOLD_SIZE) 65 #define PLAT_LMT_HOLD_BASE (PLAT_LMT_TRUSTED_MAILBOX_BASE + 8) 66 #define PLAT_LMT_HOLD_SIZE (PLATFORM_CORE_COUNT * PLAT_LMT_HOLD_ENTRY_SIZE) 67 #define PLAT_LMT_HOLD_ENTRY_SHIFT U(3) 68 #define PLAT_LMT_HOLD_ENTRY_SIZE (1 << PLAT_LMT_HOLD_ENTRY_SHIFT) 69 #define PLAT_LMT_HOLD_STATE_WAIT U(0) 70 #define PLAT_LMT_HOLD_STATE_GO U(1) 71 72 /* 73 * BL3-1 specific defines. 74 * 75 * Put BL3-1 at the top of the Trusted SRAM. BL31_BASE is calculated using the 76 * current BL3-1 debug size plus a little space for growth. 77 */ 78 #define BL31_BASE (LMT_DRAM_BASE + LMT_BL31_IMG_OFFSET) 79 #define BL31_SIZE SZ_256K 80 #define BL31_LIMIT (BL31_BASE + BL31_SIZE) 81 82 #define BL32_BASE (LMT_DRAM_BASE + LMT_BL32_IMG_OFFSET) 83 #define BL32_SIZE SZ_32M 84 #define BL32_LIMIT (BL32_BASE + BL32_SIZE) 85 86 /******************************************************************************* 87 * BL33 specific defines. 88 ******************************************************************************/ 89 #ifndef PRELOADED_BL33_BASE 90 # define PLAT_ARM_NS_IMAGE_BASE U(LMT_DRAM_BASE + LMT_BL33_IMG_OFFSET) 91 #else 92 # define PLAT_ARM_NS_IMAGE_BASE U(PRELOADED_BL33_BASE) 93 #endif 94 95 /* 96 * UART related constants 97 */ 98 #define PLAT_LMT_BOOT_UART_BASE 0x1068a000 99 #define PLAT_LMT_BOOT_UART_CLK_IN_HZ LMT_UART0_CLK_IN_HZ 100 #define PLAT_LMT_CONSOLE_BAUDRATE LMT_UART0_BAUDRATE 101 102 #define PLAT_LMT_UART1_BASE PLAT_LMT_BOOT_UART_BASE 103 #define PLAT_LMT_UART1_SIZE ULL(0x1000) 104 #define PLAT_LMT_UART1_MMAP MAP_REGION_FLAT(PLAT_LMT_UART1_BASE, \ 105 PLAT_LMT_UART1_SIZE, \ 106 MT_DEVICE | MT_RW | \ 107 MT_NS | MT_PRIVILEGED) 108 109 #define DEVICE0_BASE 0x10000000 110 #define DEVICE0_SIZE SZ_1G 111 112 /* 113 * GIC related constants 114 */ 115 #define GICD_BASE 0x00449000 116 #define GICC_BASE 0x0044a000 117 118 #define LMT_IRQ_SEC_SGI_0 8 119 #define LMT_IRQ_SEC_SGI_1 9 120 #define LMT_IRQ_SEC_SGI_2 10 121 #define LMT_IRQ_SEC_SGI_3 11 122 #define LMT_IRQ_SEC_SGI_4 12 123 #define LMT_IRQ_SEC_SGI_5 13 124 #define LMT_IRQ_SEC_SGI_6 14 125 #define LMT_IRQ_SEC_SGI_7 15 126 127 #define PLATFORM_G1S_PROPS(grp) \ 128 INTR_PROP_DESC(LMT_IRQ_SEC_SGI_0, GIC_HIGHEST_SEC_PRIORITY, \ 129 grp, GIC_INTR_CFG_EDGE), \ 130 INTR_PROP_DESC(LMT_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, \ 131 grp, GIC_INTR_CFG_EDGE), \ 132 INTR_PROP_DESC(LMT_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, \ 133 grp, GIC_INTR_CFG_EDGE), \ 134 INTR_PROP_DESC(LMT_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, \ 135 grp, GIC_INTR_CFG_EDGE), \ 136 INTR_PROP_DESC(LMT_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, \ 137 grp, GIC_INTR_CFG_EDGE), \ 138 INTR_PROP_DESC(LMT_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, \ 139 grp, GIC_INTR_CFG_EDGE), \ 140 INTR_PROP_DESC(LMT_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, \ 141 grp, GIC_INTR_CFG_EDGE), \ 142 INTR_PROP_DESC(LMT_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, \ 143 grp, GIC_INTR_CFG_EDGE) 144 145 #define PLATFORM_G0_PROPS(grp) 146 147 #define PLAT_LMT_PRIMARY_CPU 0x0 148 #define PLAT_LMT_PRIMARY_CPU_SHIFT 8 149 #define PLAT_LMT_PRIMARY_CPU_BIT_WIDTH 6 150 151 #endif /* PLATFORM_DEF_H */ 152