1*91f16700Schasinglulu /* SPDX-License-Identifier: BSD-3-Clause */ 2*91f16700Schasinglulu /* 3*91f16700Schasinglulu * Copyright (C) 2024, Charleye <wangkart@aliyun.com> 4*91f16700Schasinglulu * All rights reserved. 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #ifndef LMT_DEF_H 8*91f16700Schasinglulu #define LMT_DEF_H 9*91f16700Schasinglulu 10*91f16700Schasinglulu #define PLATFORM_NAME "lambert virt platform" 11*91f16700Schasinglulu 12*91f16700Schasinglulu /* Clock configuration */ 13*91f16700Schasinglulu #define LMT_OSC24M_CLK_IN_HZ 24000000 14*91f16700Schasinglulu 15*91f16700Schasinglulu /* UART configuration */ 16*91f16700Schasinglulu #define LMT_UART0_BAUDRATE 115200 17*91f16700Schasinglulu #define LMT_UART0_CLK_IN_HZ LMT_OSC24M_CLK_IN_HZ 18*91f16700Schasinglulu 19*91f16700Schasinglulu unsigned int lmt_calc_core_pos(u_register_t mpidr); 20*91f16700Schasinglulu void lmt_console_init(void); 21*91f16700Schasinglulu void plat_lmt_gic_init(void); 22*91f16700Schasinglulu void lmt_pwr_gic_on_finish(void); 23*91f16700Schasinglulu void lmt_pwr_gic_off(void); 24*91f16700Schasinglulu 25*91f16700Schasinglulu /* PMU register offsets for CPU*/ 26*91f16700Schasinglulu enum { 27*91f16700Schasinglulu CPU_CL0_C0_0 = 0x0214, 28*91f16700Schasinglulu CPU_CL0_C0_1 = 0x0218, 29*91f16700Schasinglulu CPU_CL0_C1_0 = 0x0220, 30*91f16700Schasinglulu CPU_CL0_C1_1 = 0x0224, 31*91f16700Schasinglulu CPU_CL0_C2_0 = 0x022c, 32*91f16700Schasinglulu CPU_CL0_C2_1 = 0x0230, 33*91f16700Schasinglulu CPU_CL0_C3_0 = 0x0238, 34*91f16700Schasinglulu CPU_CL0_C3_1 = 0x023c, 35*91f16700Schasinglulu CPU_CL1_C0_0 = 0x0240, 36*91f16700Schasinglulu CPU_CL1_C0_1 = 0x0244, 37*91f16700Schasinglulu CPU_CL1_C1_0 = 0x0248, 38*91f16700Schasinglulu CPU_CL1_C1_1 = 0x024c, 39*91f16700Schasinglulu CPU_CL1_C2_0 = 0x0250, 40*91f16700Schasinglulu CPU_CL1_C2_1 = 0x0254, 41*91f16700Schasinglulu CPU_CL1_C3_0 = 0x0258, 42*91f16700Schasinglulu CPU_CL1_C3_1 = 0x025c, 43*91f16700Schasinglulu }; 44*91f16700Schasinglulu 45*91f16700Schasinglulu #define LMT_PMU_BASE 0x100000UL 46*91f16700Schasinglulu 47*91f16700Schasinglulu #endif /* LMT_DEF_H */