1*91f16700Schasinglulu/* SPDX-License-Identifier: BSD-3-Clause */ 2*91f16700Schasinglulu/* 3*91f16700Schasinglulu * Copyright (C) 2024, Charleye <wangkart@aliyun.com> 4*91f16700Schasinglulu * All rights reserved. 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu#include <arch.h> 8*91f16700Schasinglulu#include <asm_macros.S> 9*91f16700Schasinglulu#include <assert_macros.S> 10*91f16700Schasinglulu#include <platform_def.h> 11*91f16700Schasinglulu 12*91f16700Schasinglulu .global lua_calc_core_pos 13*91f16700Schasinglulu .global plat_my_core_pos 14*91f16700Schasinglulu .global platform_mem_init 15*91f16700Schasinglulu .global plat_is_my_cpu_primary 16*91f16700Schasinglulu .global plat_secondary_cold_boot_setup 17*91f16700Schasinglulu .global plat_get_my_entrypoint 18*91f16700Schasinglulu .global plat_crash_console_init 19*91f16700Schasinglulu .global plat_crash_console_putc 20*91f16700Schasinglulu .global plat_crash_console_flush 21*91f16700Schasinglulu .global plat_report_exception 22*91f16700Schasinglulu .global plat_panic_handler 23*91f16700Schasinglulu 24*91f16700Schasinglulu.section .rodata.plat_prints, "aS" 25*91f16700Schasinglulupanic_handler_msg: 26*91f16700Schasinglulu .asciz "[PANIC HANDLER] Loop in EL3.\n" 27*91f16700Schasinglulu 28*91f16700Schasinglulufunc plat_crash_console_init 29*91f16700Schasinglulu mov_imm x0, PLAT_LUA_BOOT_UART_BASE 30*91f16700Schasinglulu mov_imm x1, PLAT_LUA_BOOT_UART_CLK_IN_HZ 31*91f16700Schasinglulu mov_imm x2, PLAT_LUA_CONSOLE_BAUDRATE 32*91f16700Schasinglulu b console_16550_core_init 33*91f16700Schasingluluendfunc plat_crash_console_init 34*91f16700Schasinglulu 35*91f16700Schasinglulufunc plat_crash_console_putc 36*91f16700Schasinglulu mov_imm x1, PLAT_LUA_BOOT_UART_BASE 37*91f16700Schasinglulu b console_16550_core_putc 38*91f16700Schasingluluendfunc plat_crash_console_putc 39*91f16700Schasinglulu 40*91f16700Schasinglulufunc plat_crash_console_flush 41*91f16700Schasinglulu ret 42*91f16700Schasingluluendfunc plat_crash_console_flush 43*91f16700Schasinglulu 44*91f16700Schasinglulufunc plat_report_exception 45*91f16700Schasinglulu ret 46*91f16700Schasingluluendfunc plat_report_exception 47*91f16700Schasinglulu 48*91f16700Schasinglulufunc plat_panic_handler 49*91f16700Schasinglulu adr x4, panic_handler_msg 50*91f16700Schasinglulu bl asm_print_str 51*91f16700Schasinglulu wfi 52*91f16700Schasinglulu b plat_panic_handler 53*91f16700Schasingluluendfunc plat_panic_handler 54*91f16700Schasinglulu 55*91f16700Schasinglulu/* 56*91f16700Schasinglulu * unsigned int lua_calc_core_pos(u_register_t mpidr) 57*91f16700Schasinglulu * core_pos = (cluster_id * max_cpus_per_cluster) + core_id 58*91f16700Schasinglulu */ 59*91f16700Schasinglulufunc lua_calc_core_pos 60*91f16700Schasinglulu and x1, x0, #MPIDR_CPU_MASK 61*91f16700Schasinglulu and x0, x0, #MPIDR_CLUSTER_MASK 62*91f16700Schasinglulu add x0, x1, x0, lsr #6 63*91f16700Schasinglulu ret 64*91f16700Schasingluluendfunc lua_calc_core_pos 65*91f16700Schasinglulu 66*91f16700Schasinglulufunc plat_my_core_pos 67*91f16700Schasinglulu mrs x0, mpidr_el1 68*91f16700Schasinglulu lsr x0, x0, #8 69*91f16700Schasinglulu b lua_calc_core_pos 70*91f16700Schasingluluendfunc plat_my_core_pos 71*91f16700Schasinglulu 72*91f16700Schasinglulufunc platform_mem_init 73*91f16700Schasinglulu ret 74*91f16700Schasingluluendfunc platform_mem_init 75*91f16700Schasinglulu 76*91f16700Schasinglulu/* 77*91f16700Schasinglulu * Secondary CPUs are placed in a holding pen, waiting for their mailbox 78*91f16700Schasinglulu * to be populated. Note that all CPUs share the same mailbox ; therefore, 79*91f16700Schasinglulu * populating it will release all CPUs from their holding pen. If 80*91f16700Schasinglulu * finer-grained control is needed then this should be handled in the 81*91f16700Schasinglulu * code that secondary CPUs jump to. 82*91f16700Schasinglulu */ 83*91f16700Schasinglulufunc plat_secondary_cold_boot_setup 84*91f16700Schasinglulu /* Calculate address of our hold entry */ 85*91f16700Schasinglulu bl plat_my_core_pos 86*91f16700Schasinglulu lsl x0, x0, #PLAT_LUA_HOLD_ENTRY_SHIFT 87*91f16700Schasinglulu mov_imm x2, PLAT_LUA_HOLD_BASE 88*91f16700Schasinglulu 89*91f16700Schasinglulu /* Wait until we have a go */ 90*91f16700Schasinglulupoll_mailbox: 91*91f16700Schasinglulu ldr x1, [x2, x0] 92*91f16700Schasinglulu cbz x1, 1f 93*91f16700Schasinglulu 94*91f16700Schasinglulu /* Clear the mailbox again ready for next time. */ 95*91f16700Schasinglulu mov x1, #PLAT_LUA_HOLD_STATE_WAIT 96*91f16700Schasinglulu str x1, [x2, x0] 97*91f16700Schasinglulu 98*91f16700Schasinglulu /* Jump to the provided entrypoint. */ 99*91f16700Schasinglulu mov_imm x0, PLAT_LUA_TRUSTED_MAILBOX_BASE 100*91f16700Schasinglulu ldr x1, [x0] 101*91f16700Schasinglulu br x1 102*91f16700Schasinglulu1: 103*91f16700Schasinglulu wfe 104*91f16700Schasinglulu b poll_mailbox 105*91f16700Schasingluluendfunc plat_secondary_cold_boot_setup 106*91f16700Schasinglulu 107*91f16700Schasinglulufunc plat_get_my_entrypoint 108*91f16700Schasinglulu /* TODO support warm boot */ 109*91f16700Schasinglulu mov x0, #0 110*91f16700Schasinglulu ret 111*91f16700Schasingluluendfunc plat_get_my_entrypoint 112*91f16700Schasinglulu 113*91f16700Schasinglulu/* 114*91f16700Schasinglulu * Find out whether the current cpu is the primary 115*91f16700Schasinglulu * cpu (applicable only after a cold boot) 116*91f16700Schasinglulu */ 117*91f16700Schasinglulufunc plat_is_my_cpu_primary 118*91f16700Schasinglulu mrs x0, mpidr_el1 119*91f16700Schasinglulu and x0, x0, #(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK) 120*91f16700Schasinglulu cmp x0, #PLAT_LUA_PRIMARY_CPU 121*91f16700Schasinglulu cset w0, eq 122*91f16700Schasinglulu ret 123*91f16700Schasingluluendfunc plat_is_my_cpu_primary 124