1*91f16700Schasinglulu /* SPDX-License-Identifier: BSD-3-Clause */ 2*91f16700Schasinglulu /* 3*91f16700Schasinglulu * Copyright (C) 2024, Charleye <wangkart@aliyun.com> 4*91f16700Schasinglulu * All rights reserved. 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #include <drivers/arm/gicv2.h> 8*91f16700Schasinglulu #include <drivers/arm/gic_common.h> 9*91f16700Schasinglulu #include <platform_def.h> 10*91f16700Schasinglulu 11*91f16700Schasinglulu static const interrupt_prop_t lua_interrupt_props[] = { 12*91f16700Schasinglulu #if ENABLE_FEAT_RAS && FFH_SUPPORT 13*91f16700Schasinglulu PLATFORM_RAS_G0_PROPS(GICV2_INTR_GROUP0), 14*91f16700Schasinglulu #endif 15*91f16700Schasinglulu PLATFORM_G1S_PROPS(GICV2_INTR_GROUP0), 16*91f16700Schasinglulu PLATFORM_FAB_PERIPH_G0_PROPS(GICV2_INTR_GROUP0), 17*91f16700Schasinglulu #if LUA_SEC_UART1_IRQ 18*91f16700Schasinglulu PLATFORM_UART1_G0_PROPS(GICV2_INTR_GROUP0) 19*91f16700Schasinglulu #endif 20*91f16700Schasinglulu }; 21*91f16700Schasinglulu 22*91f16700Schasinglulu static unsigned int lua_target_masks[] = { 23*91f16700Schasinglulu BIT_32(0), 24*91f16700Schasinglulu BIT_32(1), 25*91f16700Schasinglulu BIT_32(2), 26*91f16700Schasinglulu BIT_32(3), 27*91f16700Schasinglulu }; 28*91f16700Schasinglulu 29*91f16700Schasinglulu static const struct gicv2_driver_data plat_gicv2_driver_data = { 30*91f16700Schasinglulu .gicd_base = GICD_BASE, 31*91f16700Schasinglulu .gicc_base = GICC_BASE, 32*91f16700Schasinglulu .target_masks = lua_target_masks, 33*91f16700Schasinglulu .target_masks_num = ARRAY_SIZE(lua_target_masks), 34*91f16700Schasinglulu .interrupt_props = lua_interrupt_props, 35*91f16700Schasinglulu .interrupt_props_num = ARRAY_SIZE(lua_interrupt_props), 36*91f16700Schasinglulu }; 37*91f16700Schasinglulu 38*91f16700Schasinglulu static inline void lua_ras_intr_configure(void) 39*91f16700Schasinglulu { 40*91f16700Schasinglulu gicv2_set_spi_routing(PLAT_LUA_CPU0_ERRIRQ, 0); 41*91f16700Schasinglulu gicv2_set_spi_routing(PLAT_LUA_CPU0_FAULTIRQ, 0); 42*91f16700Schasinglulu 43*91f16700Schasinglulu gicv2_set_spi_routing(PLAT_LUA_CPU1_ERRIRQ, 1); 44*91f16700Schasinglulu gicv2_set_spi_routing(PLAT_LUA_CPU1_FAULTIRQ, 1); 45*91f16700Schasinglulu 46*91f16700Schasinglulu gicv2_set_spi_routing(PLAT_LUA_CPU2_ERRIRQ, 2); 47*91f16700Schasinglulu gicv2_set_spi_routing(PLAT_LUA_CPU2_FAULTIRQ, 2); 48*91f16700Schasinglulu 49*91f16700Schasinglulu gicv2_set_spi_routing(PLAT_LUA_CPU3_ERRIRQ, 3); 50*91f16700Schasinglulu gicv2_set_spi_routing(PLAT_LUA_CPU3_FAULTIRQ, 3); 51*91f16700Schasinglulu } 52*91f16700Schasinglulu 53*91f16700Schasinglulu void plat_lua_gic_init(void) 54*91f16700Schasinglulu { 55*91f16700Schasinglulu /* Initialize the gic cpu and distributor interfaces */ 56*91f16700Schasinglulu gicv2_driver_init(&plat_gicv2_driver_data); 57*91f16700Schasinglulu gicv2_distif_init(); 58*91f16700Schasinglulu gicv2_pcpu_distif_init(); 59*91f16700Schasinglulu gicv2_cpuif_enable(); 60*91f16700Schasinglulu #if ENABLE_FEAT_RAS && FFH_SUPPORT 61*91f16700Schasinglulu lua_ras_intr_configure(); 62*91f16700Schasinglulu #endif 63*91f16700Schasinglulu } 64*91f16700Schasinglulu 65*91f16700Schasinglulu void lua_pwr_gic_on_finish(void) 66*91f16700Schasinglulu { 67*91f16700Schasinglulu /* TODO: This setup is needed only after a cold boot */ 68*91f16700Schasinglulu gicv2_pcpu_distif_init(); 69*91f16700Schasinglulu 70*91f16700Schasinglulu /* Enable the gic cpu interface */ 71*91f16700Schasinglulu gicv2_cpuif_enable(); 72*91f16700Schasinglulu } 73*91f16700Schasinglulu 74*91f16700Schasinglulu void lua_pwr_gic_off(void) 75*91f16700Schasinglulu { 76*91f16700Schasinglulu gicv2_cpuif_disable(); 77*91f16700Schasinglulu } 78