1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2023, Aspeed Technology Inc. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #include <arch.h> 8*91f16700Schasinglulu #include <lib/psci/psci.h> 9*91f16700Schasinglulu #include <platform_def.h> 10*91f16700Schasinglulu 11*91f16700Schasinglulu static const unsigned char ast2700_power_domain_tree_desc[] = { 12*91f16700Schasinglulu PLATFORM_SYSTEM_COUNT, 13*91f16700Schasinglulu PLATFORM_CORE_COUNT_PER_CLUSTER, 14*91f16700Schasinglulu }; 15*91f16700Schasinglulu 16*91f16700Schasinglulu const unsigned char *plat_get_power_domain_tree_desc(void) 17*91f16700Schasinglulu { 18*91f16700Schasinglulu return ast2700_power_domain_tree_desc; 19*91f16700Schasinglulu } 20*91f16700Schasinglulu 21*91f16700Schasinglulu unsigned int plat_core_pos_by_mpidr(u_register_t mpidr) 22*91f16700Schasinglulu { 23*91f16700Schasinglulu unsigned int cluster_id, cpu_id; 24*91f16700Schasinglulu 25*91f16700Schasinglulu mpidr &= MPIDR_AFFINITY_MASK; 26*91f16700Schasinglulu 27*91f16700Schasinglulu if (mpidr & ~(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK)) { 28*91f16700Schasinglulu return -1; 29*91f16700Schasinglulu } 30*91f16700Schasinglulu 31*91f16700Schasinglulu cluster_id = (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK; 32*91f16700Schasinglulu cpu_id = (mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK; 33*91f16700Schasinglulu 34*91f16700Schasinglulu if (cluster_id >= PLATFORM_CLUSTER_COUNT) { 35*91f16700Schasinglulu return -1; 36*91f16700Schasinglulu } 37*91f16700Schasinglulu 38*91f16700Schasinglulu if (cpu_id >= PLATFORM_CORE_COUNT_PER_CLUSTER) { 39*91f16700Schasinglulu return -1; 40*91f16700Schasinglulu } 41*91f16700Schasinglulu 42*91f16700Schasinglulu return (cluster_id * PLATFORM_CORE_COUNT_PER_CLUSTER) + cpu_id; 43*91f16700Schasinglulu } 44