1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2023, Aspeed Technology Inc. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #ifndef PLATFORM_REG_H 8*91f16700Schasinglulu #define PLATFORM_REG_H 9*91f16700Schasinglulu 10*91f16700Schasinglulu /* GIC */ 11*91f16700Schasinglulu #define GICD_BASE U(0x12200000) 12*91f16700Schasinglulu #define GICD_SIZE U(0x10000) 13*91f16700Schasinglulu #define GICR_BASE U(0x12280000) 14*91f16700Schasinglulu #define GICR_SIZE U(0x100000) 15*91f16700Schasinglulu 16*91f16700Schasinglulu /* UART */ 17*91f16700Schasinglulu #define UART_BASE U(0x14c33000) 18*91f16700Schasinglulu #define UART12_BASE (UART_BASE + 0xb00) 19*91f16700Schasinglulu 20*91f16700Schasinglulu /* CPU-die SCU */ 21*91f16700Schasinglulu #define SCU_CPU_BASE U(0x12c02000) 22*91f16700Schasinglulu #define SCU_CPU_SMP_EP0 (SCU_CPU_BASE + 0x780) 23*91f16700Schasinglulu #define SCU_CPU_SMP_EP1 (SCU_CPU_BASE + 0x788) 24*91f16700Schasinglulu #define SCU_CPU_SMP_EP2 (SCU_CPU_BASE + 0x790) 25*91f16700Schasinglulu #define SCU_CPU_SMP_EP3 (SCU_CPU_BASE + 0x798) 26*91f16700Schasinglulu 27*91f16700Schasinglulu #endif /* PLATFORM_REG_H */ 28