1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2023, Aspeed Technology Inc. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #ifndef PLATFORM_DEF_H 8*91f16700Schasinglulu #define PLATFORM_DEF_H 9*91f16700Schasinglulu 10*91f16700Schasinglulu #include <arch.h> 11*91f16700Schasinglulu #include <plat/common/common_def.h> 12*91f16700Schasinglulu #include <platform_reg.h> 13*91f16700Schasinglulu 14*91f16700Schasinglulu #define PLATFORM_STACK_SIZE UL(0x1000) 15*91f16700Schasinglulu 16*91f16700Schasinglulu /* cpu topology */ 17*91f16700Schasinglulu #define PLATFORM_SYSTEM_COUNT U(1) 18*91f16700Schasinglulu #define PLATFORM_CLUSTER_COUNT U(1) 19*91f16700Schasinglulu #define PLATFORM_CORE_PRIMARY U(0) 20*91f16700Schasinglulu #define PLATFORM_CORE_COUNT_PER_CLUSTER U(4) 21*91f16700Schasinglulu #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER_COUNT * \ 22*91f16700Schasinglulu PLATFORM_CORE_COUNT_PER_CLUSTER) 23*91f16700Schasinglulu 24*91f16700Schasinglulu /* arch timer */ 25*91f16700Schasinglulu #define PLAT_SYSCNT_CLKIN_HZ U(1600000000) 26*91f16700Schasinglulu 27*91f16700Schasinglulu /* power domain */ 28*91f16700Schasinglulu #define PLAT_MAX_PWR_LVL U(1) 29*91f16700Schasinglulu #define PLAT_NUM_PWR_DOMAINS U(5) 30*91f16700Schasinglulu #define PLAT_MAX_RET_STATE U(1) 31*91f16700Schasinglulu #define PLAT_MAX_OFF_STATE U(2) 32*91f16700Schasinglulu 33*91f16700Schasinglulu /* cache line size */ 34*91f16700Schasinglulu #define CACHE_WRITEBACK_SHIFT U(6) 35*91f16700Schasinglulu #define CACHE_WRITEBACK_GRANULE (U(1) << CACHE_WRITEBACK_SHIFT) 36*91f16700Schasinglulu 37*91f16700Schasinglulu /* translation tables */ 38*91f16700Schasinglulu #define PLAT_PHY_ADDR_SPACE_SIZE (ULL(1) << 36) 39*91f16700Schasinglulu #define PLAT_VIRT_ADDR_SPACE_SIZE (ULL(1) << 40) 40*91f16700Schasinglulu #define MAX_XLAT_TABLES U(8) 41*91f16700Schasinglulu #define MAX_MMAP_REGIONS U(32) 42*91f16700Schasinglulu 43*91f16700Schasinglulu /* BL31 region */ 44*91f16700Schasinglulu #define BL31_BASE ULL(0x430000000) 45*91f16700Schasinglulu #define BL31_SIZE SZ_512K 46*91f16700Schasinglulu #define BL31_LIMIT (BL31_BASE + BL31_SIZE) 47*91f16700Schasinglulu 48*91f16700Schasinglulu /* BL32 region */ 49*91f16700Schasinglulu #define BL32_BASE BL31_LIMIT 50*91f16700Schasinglulu #define BL32_SIZE SZ_16M 51*91f16700Schasinglulu #define BL32_LIMIT (BL32_BASE + BL32_SIZE) 52*91f16700Schasinglulu 53*91f16700Schasinglulu /* console */ 54*91f16700Schasinglulu #define CONSOLE_UART_BASE UART12_BASE 55*91f16700Schasinglulu #define CONSOLE_UART_CLKIN_HZ U(1846153) 56*91f16700Schasinglulu #define CONSOLE_UART_BAUDRATE U(115200) 57*91f16700Schasinglulu 58*91f16700Schasinglulu #endif /* PLATFORM_DEF_H */ 59