1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #include <platform_def.h> 8*91f16700Schasinglulu 9*91f16700Schasinglulu #include <drivers/arm/nic_400.h> 10*91f16700Schasinglulu #include <lib/mmio.h> 11*91f16700Schasinglulu #include <plat/arm/soc/common/soc_css.h> 12*91f16700Schasinglulu 13*91f16700Schasinglulu void soc_css_init_nic400(void) 14*91f16700Schasinglulu { 15*91f16700Schasinglulu /* 16*91f16700Schasinglulu * NIC-400 Access Control Initialization 17*91f16700Schasinglulu * 18*91f16700Schasinglulu * Define access privileges by setting each corresponding bit to: 19*91f16700Schasinglulu * 0 = Secure access only 20*91f16700Schasinglulu * 1 = Non-secure access allowed 21*91f16700Schasinglulu */ 22*91f16700Schasinglulu 23*91f16700Schasinglulu /* 24*91f16700Schasinglulu * Allow non-secure access to some SOC regions, excluding UART1, which 25*91f16700Schasinglulu * remains secure (unless CSS_NON_SECURE_UART is set). 26*91f16700Schasinglulu * Note: This is the NIC-400 device on the SOC 27*91f16700Schasinglulu */ 28*91f16700Schasinglulu mmio_write_32(SOC_CSS_NIC400_BASE + 29*91f16700Schasinglulu NIC400_ADDR_CTRL_SECURITY_REG(SOC_CSS_NIC400_USB_EHCI), ~0); 30*91f16700Schasinglulu mmio_write_32(SOC_CSS_NIC400_BASE + 31*91f16700Schasinglulu NIC400_ADDR_CTRL_SECURITY_REG(SOC_CSS_NIC400_TLX_MASTER), ~0); 32*91f16700Schasinglulu mmio_write_32(SOC_CSS_NIC400_BASE + 33*91f16700Schasinglulu NIC400_ADDR_CTRL_SECURITY_REG(SOC_CSS_NIC400_USB_OHCI), ~0); 34*91f16700Schasinglulu mmio_write_32(SOC_CSS_NIC400_BASE + 35*91f16700Schasinglulu NIC400_ADDR_CTRL_SECURITY_REG(SOC_CSS_NIC400_PL354_SMC), ~0); 36*91f16700Schasinglulu mmio_write_32(SOC_CSS_NIC400_BASE + 37*91f16700Schasinglulu NIC400_ADDR_CTRL_SECURITY_REG(SOC_CSS_NIC400_APB4_BRIDGE), ~0); 38*91f16700Schasinglulu #if CSS_NON_SECURE_UART 39*91f16700Schasinglulu /* Configure UART for non-secure access */ 40*91f16700Schasinglulu mmio_write_32(SOC_CSS_NIC400_BASE + 41*91f16700Schasinglulu NIC400_ADDR_CTRL_SECURITY_REG(SOC_CSS_NIC400_BOOTSEC_BRIDGE), ~0); 42*91f16700Schasinglulu #else 43*91f16700Schasinglulu mmio_write_32(SOC_CSS_NIC400_BASE + 44*91f16700Schasinglulu NIC400_ADDR_CTRL_SECURITY_REG(SOC_CSS_NIC400_BOOTSEC_BRIDGE), 45*91f16700Schasinglulu ~SOC_CSS_NIC400_BOOTSEC_BRIDGE_UART1); 46*91f16700Schasinglulu #endif /* CSS_NON_SECURE_UART */ 47*91f16700Schasinglulu 48*91f16700Schasinglulu } 49*91f16700Schasinglulu 50*91f16700Schasinglulu 51*91f16700Schasinglulu #define PCIE_SECURE_REG 0x3000 52*91f16700Schasinglulu /* Mask uses REG and MEM access bits */ 53*91f16700Schasinglulu #define PCIE_SEC_ACCESS_MASK ((1 << 0) | (1 << 1)) 54*91f16700Schasinglulu 55*91f16700Schasinglulu void soc_css_init_pcie(void) 56*91f16700Schasinglulu { 57*91f16700Schasinglulu #if !PLAT_juno 58*91f16700Schasinglulu /* 59*91f16700Schasinglulu * Do not initialize PCIe in emulator environment. 60*91f16700Schasinglulu * Platform ID register not supported on Juno 61*91f16700Schasinglulu */ 62*91f16700Schasinglulu if (BOARD_CSS_GET_PLAT_TYPE(BOARD_CSS_PLAT_ID_REG_ADDR) == 63*91f16700Schasinglulu BOARD_CSS_PLAT_TYPE_EMULATOR) 64*91f16700Schasinglulu return; 65*91f16700Schasinglulu #endif /* PLAT_juno */ 66*91f16700Schasinglulu 67*91f16700Schasinglulu /* 68*91f16700Schasinglulu * PCIE Root Complex Security settings to enable non-secure 69*91f16700Schasinglulu * access to config registers. 70*91f16700Schasinglulu */ 71*91f16700Schasinglulu mmio_write_32(SOC_CSS_PCIE_CONTROL_BASE + PCIE_SECURE_REG, 72*91f16700Schasinglulu PCIE_SEC_ACCESS_MASK); 73*91f16700Schasinglulu } 74