1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #ifndef SGI_DMC620_TZC_REGIONS_H 8*91f16700Schasinglulu #define SGI_DMC620_TZC_REGIONS_H 9*91f16700Schasinglulu 10*91f16700Schasinglulu #include <drivers/arm/tzc_dmc620.h> 11*91f16700Schasinglulu 12*91f16700Schasinglulu #if SPM_MM 13*91f16700Schasinglulu #define CSS_SGI_DMC620_TZC_REGIONS_DEF \ 14*91f16700Schasinglulu { \ 15*91f16700Schasinglulu .region_base = ARM_AP_TZC_DRAM1_BASE, \ 16*91f16700Schasinglulu .region_top = PLAT_SP_IMAGE_NS_BUF_BASE - 1, \ 17*91f16700Schasinglulu .sec_attr = TZC_DMC620_REGION_S_RDWR \ 18*91f16700Schasinglulu }, { \ 19*91f16700Schasinglulu .region_base = PLAT_SP_IMAGE_NS_BUF_BASE, \ 20*91f16700Schasinglulu .region_top = PLAT_ARM_SP_IMAGE_STACK_BASE - 1, \ 21*91f16700Schasinglulu .sec_attr = TZC_DMC620_REGION_S_NS_RDWR \ 22*91f16700Schasinglulu }, { \ 23*91f16700Schasinglulu .region_base = PLAT_ARM_SP_IMAGE_STACK_BASE, \ 24*91f16700Schasinglulu .region_top = ARM_AP_TZC_DRAM1_END, \ 25*91f16700Schasinglulu .sec_attr = TZC_DMC620_REGION_S_RDWR \ 26*91f16700Schasinglulu } 27*91f16700Schasinglulu #else 28*91f16700Schasinglulu #define CSS_SGI_DMC620_TZC_REGIONS_DEF \ 29*91f16700Schasinglulu { \ 30*91f16700Schasinglulu .region_base = ARM_AP_TZC_DRAM1_BASE, \ 31*91f16700Schasinglulu .region_top = ARM_AP_TZC_DRAM1_END, \ 32*91f16700Schasinglulu .sec_attr = TZC_DMC620_REGION_S_RDWR \ 33*91f16700Schasinglulu } 34*91f16700Schasinglulu #endif /* SPM_MM */ 35*91f16700Schasinglulu 36*91f16700Schasinglulu #endif /* SGI_DMC620_TZC_REGIONS_H */ 37