1*91f16700Schasinglulu/* 2*91f16700Schasinglulu * Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu#include <arch.h> 8*91f16700Schasinglulu#include <asm_macros.S> 9*91f16700Schasinglulu#include <platform_def.h> 10*91f16700Schasinglulu#include <cortex_a75.h> 11*91f16700Schasinglulu#include <neoverse_n1.h> 12*91f16700Schasinglulu#include <neoverse_v1.h> 13*91f16700Schasinglulu#include <neoverse_n2.h> 14*91f16700Schasinglulu#include <cpu_macros.S> 15*91f16700Schasinglulu 16*91f16700Schasinglulu .globl plat_arm_calc_core_pos 17*91f16700Schasinglulu .globl plat_reset_handler 18*91f16700Schasinglulu 19*91f16700Schasinglulu /* ----------------------------------------------------- 20*91f16700Schasinglulu * unsigned int plat_arm_calc_core_pos(u_register_t mpidr) 21*91f16700Schasinglulu * 22*91f16700Schasinglulu * Helper function to calculate the core position. 23*91f16700Schasinglulu * (ChipId * PLAT_ARM_CLUSTER_COUNT * 24*91f16700Schasinglulu * CSS_SGI_MAX_CPUS_PER_CLUSTER * CSS_SGI_MAX_PE_PER_CPU) + 25*91f16700Schasinglulu * (ClusterId * CSS_SGI_MAX_CPUS_PER_CLUSTER * CSS_SGI_MAX_PE_PER_CPU) + 26*91f16700Schasinglulu * (CPUId * CSS_SGI_MAX_PE_PER_CPU) + 27*91f16700Schasinglulu * ThreadId 28*91f16700Schasinglulu * 29*91f16700Schasinglulu * which can be simplified as: 30*91f16700Schasinglulu * 31*91f16700Schasinglulu * ((((ChipId * PLAT_ARM_CLUSTER_COUNT) + ClusterId) * 32*91f16700Schasinglulu * CSS_SGI_MAX_CPUS_PER_CLUSTER) + CPUId) * CSS_SGI_MAX_PE_PER_CPU + 33*91f16700Schasinglulu * ThreadId 34*91f16700Schasinglulu * ------------------------------------------------------ 35*91f16700Schasinglulu */ 36*91f16700Schasinglulu 37*91f16700Schasinglulufunc plat_arm_calc_core_pos 38*91f16700Schasinglulu mov x4, x0 39*91f16700Schasinglulu 40*91f16700Schasinglulu /* 41*91f16700Schasinglulu * The MT bit in MPIDR is always set for SGI platforms 42*91f16700Schasinglulu * and the affinity level 0 corresponds to thread affinity level. 43*91f16700Schasinglulu */ 44*91f16700Schasinglulu 45*91f16700Schasinglulu /* Extract individual affinity fields from MPIDR */ 46*91f16700Schasinglulu ubfx x0, x4, #MPIDR_AFF0_SHIFT, #MPIDR_AFFINITY_BITS 47*91f16700Schasinglulu ubfx x1, x4, #MPIDR_AFF1_SHIFT, #MPIDR_AFFINITY_BITS 48*91f16700Schasinglulu ubfx x2, x4, #MPIDR_AFF2_SHIFT, #MPIDR_AFFINITY_BITS 49*91f16700Schasinglulu ubfx x3, x4, #MPIDR_AFF3_SHIFT, #MPIDR_AFFINITY_BITS 50*91f16700Schasinglulu 51*91f16700Schasinglulu /* Compute linear position */ 52*91f16700Schasinglulu mov x4, #PLAT_ARM_CLUSTER_COUNT 53*91f16700Schasinglulu madd x2, x3, x4, x2 54*91f16700Schasinglulu mov x4, #CSS_SGI_MAX_CPUS_PER_CLUSTER 55*91f16700Schasinglulu madd x1, x2, x4, x1 56*91f16700Schasinglulu mov x4, #CSS_SGI_MAX_PE_PER_CPU 57*91f16700Schasinglulu madd x0, x1, x4, x0 58*91f16700Schasinglulu ret 59*91f16700Schasingluluendfunc plat_arm_calc_core_pos 60*91f16700Schasinglulu 61*91f16700Schasinglulu /* ----------------------------------------------------- 62*91f16700Schasinglulu * void plat_reset_handler(void); 63*91f16700Schasinglulu * 64*91f16700Schasinglulu * Determine the CPU MIDR and disable power down bit for 65*91f16700Schasinglulu * that CPU. 66*91f16700Schasinglulu * ----------------------------------------------------- 67*91f16700Schasinglulu */ 68*91f16700Schasinglulufunc plat_reset_handler 69*91f16700Schasinglulu jump_if_cpu_midr CORTEX_A75_MIDR, A75 70*91f16700Schasinglulu jump_if_cpu_midr NEOVERSE_N1_MIDR, N1 71*91f16700Schasinglulu jump_if_cpu_midr NEOVERSE_V1_MIDR, V1 72*91f16700Schasinglulu jump_if_cpu_midr NEOVERSE_N2_MIDR, N2 73*91f16700Schasinglulu ret 74*91f16700Schasinglulu 75*91f16700Schasinglulu /* ----------------------------------------------------- 76*91f16700Schasinglulu * Disable CPU power down bit in power control register 77*91f16700Schasinglulu * ----------------------------------------------------- 78*91f16700Schasinglulu */ 79*91f16700SchasingluluA75: 80*91f16700Schasinglulu mrs x0, CORTEX_A75_CPUPWRCTLR_EL1 81*91f16700Schasinglulu bic x0, x0, #CORTEX_A75_CORE_PWRDN_EN_MASK 82*91f16700Schasinglulu msr CORTEX_A75_CPUPWRCTLR_EL1, x0 83*91f16700Schasinglulu isb 84*91f16700Schasinglulu ret 85*91f16700Schasinglulu 86*91f16700SchasingluluN1: 87*91f16700Schasinglulu mrs x0, NEOVERSE_N1_CPUPWRCTLR_EL1 88*91f16700Schasinglulu bic x0, x0, #NEOVERSE_N1_CORE_PWRDN_EN_MASK 89*91f16700Schasinglulu msr NEOVERSE_N1_CPUPWRCTLR_EL1, x0 90*91f16700Schasinglulu isb 91*91f16700Schasinglulu ret 92*91f16700Schasinglulu 93*91f16700SchasingluluV1: 94*91f16700Schasinglulu mrs x0, NEOVERSE_V1_CPUPWRCTLR_EL1 95*91f16700Schasinglulu bic x0, x0, #NEOVERSE_V1_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 96*91f16700Schasinglulu msr NEOVERSE_V1_CPUPWRCTLR_EL1, x0 97*91f16700Schasinglulu isb 98*91f16700Schasinglulu ret 99*91f16700Schasinglulu 100*91f16700SchasingluluN2: 101*91f16700Schasinglulu mrs x0, NEOVERSE_N2_CPUPWRCTLR_EL1 102*91f16700Schasinglulu bic x0, x0, #NEOVERSE_N2_CORE_PWRDN_EN_BIT 103*91f16700Schasinglulu msr NEOVERSE_N2_CPUPWRCTLR_EL1, x0 104*91f16700Schasinglulu isb 105*91f16700Schasinglulu ret 106*91f16700Schasingluluendfunc plat_reset_handler 107