1*91f16700Schasinglulu/* 2*91f16700Schasinglulu * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu#include <arch.h> 8*91f16700Schasinglulu#include <asm_macros.S> 9*91f16700Schasinglulu#include <cpu_macros.S> 10*91f16700Schasinglulu#include <platform_def.h> 11*91f16700Schasinglulu 12*91f16700Schasinglulu .weak plat_secondary_cold_boot_setup 13*91f16700Schasinglulu .weak plat_get_my_entrypoint 14*91f16700Schasinglulu .globl css_calc_core_pos_swap_cluster 15*91f16700Schasinglulu .weak plat_is_my_cpu_primary 16*91f16700Schasinglulu 17*91f16700Schasinglulu /* --------------------------------------------------------------------- 18*91f16700Schasinglulu * void plat_secondary_cold_boot_setup(void); 19*91f16700Schasinglulu * In the normal boot flow, cold-booting secondary 20*91f16700Schasinglulu * CPUs is not yet implemented and they panic. 21*91f16700Schasinglulu * --------------------------------------------------------------------- 22*91f16700Schasinglulu */ 23*91f16700Schasinglulufunc plat_secondary_cold_boot_setup 24*91f16700Schasinglulu /* TODO: Implement secondary CPU cold boot setup on CSS platforms */ 25*91f16700Schasinglulucb_panic: 26*91f16700Schasinglulu b cb_panic 27*91f16700Schasingluluendfunc plat_secondary_cold_boot_setup 28*91f16700Schasinglulu 29*91f16700Schasinglulu /* --------------------------------------------------------------------- 30*91f16700Schasinglulu * uintptr_t plat_get_my_entrypoint (void); 31*91f16700Schasinglulu * 32*91f16700Schasinglulu * Main job of this routine is to distinguish between a cold and a warm 33*91f16700Schasinglulu * boot. On CSS platforms, this distinction is based on the contents of 34*91f16700Schasinglulu * the Trusted Mailbox. It is initialised to zero by the SCP before the 35*91f16700Schasinglulu * AP cores are released from reset. Therefore, a zero mailbox means 36*91f16700Schasinglulu * it's a cold reset. 37*91f16700Schasinglulu * 38*91f16700Schasinglulu * This functions returns the contents of the mailbox, i.e.: 39*91f16700Schasinglulu * - 0 for a cold boot; 40*91f16700Schasinglulu * - the warm boot entrypoint for a warm boot. 41*91f16700Schasinglulu * --------------------------------------------------------------------- 42*91f16700Schasinglulu */ 43*91f16700Schasinglulufunc plat_get_my_entrypoint 44*91f16700Schasinglulu ldr r0, =PLAT_ARM_TRUSTED_MAILBOX_BASE 45*91f16700Schasinglulu ldr r0, [r0] 46*91f16700Schasinglulu bx lr 47*91f16700Schasingluluendfunc plat_get_my_entrypoint 48*91f16700Schasinglulu 49*91f16700Schasinglulu /* ----------------------------------------------------------- 50*91f16700Schasinglulu * unsigned int css_calc_core_pos_swap_cluster(u_register_t mpidr) 51*91f16700Schasinglulu * Utility function to calculate the core position by 52*91f16700Schasinglulu * swapping the cluster order. This is necessary in order to 53*91f16700Schasinglulu * match the format of the boot information passed by the SCP 54*91f16700Schasinglulu * and read in plat_is_my_cpu_primary below. 55*91f16700Schasinglulu * ----------------------------------------------------------- 56*91f16700Schasinglulu */ 57*91f16700Schasinglulufunc css_calc_core_pos_swap_cluster 58*91f16700Schasinglulu and r1, r0, #MPIDR_CPU_MASK 59*91f16700Schasinglulu and r0, r0, #MPIDR_CLUSTER_MASK 60*91f16700Schasinglulu eor r0, r0, #(1 << MPIDR_AFFINITY_BITS) // swap cluster order 61*91f16700Schasinglulu add r0, r1, r0, LSR #6 62*91f16700Schasinglulu bx lr 63*91f16700Schasingluluendfunc css_calc_core_pos_swap_cluster 64*91f16700Schasinglulu 65*91f16700Schasinglulu /* ----------------------------------------------------- 66*91f16700Schasinglulu * unsigned int plat_is_my_cpu_primary (void); 67*91f16700Schasinglulu * 68*91f16700Schasinglulu * Find out whether the current cpu is the primary 69*91f16700Schasinglulu * cpu (applicable ony after a cold boot) 70*91f16700Schasinglulu * ----------------------------------------------------- 71*91f16700Schasinglulu */ 72*91f16700Schasinglulu#if CSS_USE_SCMI_SDS_DRIVER 73*91f16700Schasinglulufunc plat_is_my_cpu_primary 74*91f16700Schasinglulu mov r10, lr 75*91f16700Schasinglulu bl plat_my_core_pos 76*91f16700Schasinglulu mov r4, r0 77*91f16700Schasinglulu bl sds_get_primary_cpu_id 78*91f16700Schasinglulu /* Check for error */ 79*91f16700Schasinglulu mov r1, #0xffffffff 80*91f16700Schasinglulu cmp r0, r1 81*91f16700Schasinglulu beq 1f 82*91f16700Schasinglulu cmp r0, r4 83*91f16700Schasinglulu moveq r0, #1 84*91f16700Schasinglulu movne r0, #0 85*91f16700Schasinglulu bx r10 86*91f16700Schasinglulu1: 87*91f16700Schasinglulu no_ret plat_panic_handler 88*91f16700Schasingluluendfunc plat_is_my_cpu_primary 89*91f16700Schasinglulu#else 90*91f16700Schasinglulufunc plat_is_my_cpu_primary 91*91f16700Schasinglulu mov r10, lr 92*91f16700Schasinglulu bl plat_my_core_pos 93*91f16700Schasinglulu ldr r1, =SCP_BOOT_CFG_ADDR 94*91f16700Schasinglulu ldr r1, [r1] 95*91f16700Schasinglulu ubfx r1, r1, #PLAT_CSS_PRIMARY_CPU_SHIFT, \ 96*91f16700Schasinglulu #PLAT_CSS_PRIMARY_CPU_BIT_WIDTH 97*91f16700Schasinglulu cmp r0, r1 98*91f16700Schasinglulu moveq r0, #1 99*91f16700Schasinglulu movne r0, #0 100*91f16700Schasinglulu bx r10 101*91f16700Schasingluluendfunc plat_is_my_cpu_primary 102*91f16700Schasinglulu#endif 103