1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #include <platform_def.h> 8*91f16700Schasinglulu 9*91f16700Schasinglulu #include <arch.h> 10*91f16700Schasinglulu #include <plat/arm/common/plat_arm.h> 11*91f16700Schasinglulu 12*91f16700Schasinglulu /******************************************************************************* 13*91f16700Schasinglulu * This function validates an MPIDR by checking whether it falls within the 14*91f16700Schasinglulu * acceptable bounds. An error code (-1) is returned if an incorrect mpidr 15*91f16700Schasinglulu * is passed. 16*91f16700Schasinglulu ******************************************************************************/ 17*91f16700Schasinglulu int arm_check_mpidr(u_register_t mpidr) 18*91f16700Schasinglulu { 19*91f16700Schasinglulu unsigned int cluster_id, cpu_id; 20*91f16700Schasinglulu uint64_t valid_mask; 21*91f16700Schasinglulu 22*91f16700Schasinglulu #if ARM_PLAT_MT 23*91f16700Schasinglulu unsigned int pe_id; 24*91f16700Schasinglulu 25*91f16700Schasinglulu valid_mask = ~(MPIDR_AFFLVL_MASK | 26*91f16700Schasinglulu (MPIDR_AFFLVL_MASK << MPIDR_AFF1_SHIFT) | 27*91f16700Schasinglulu (MPIDR_AFFLVL_MASK << MPIDR_AFF2_SHIFT) | 28*91f16700Schasinglulu (MPIDR_AFFLVL_MASK << MPIDR_AFF3_SHIFT)); 29*91f16700Schasinglulu cluster_id = (mpidr >> MPIDR_AFF2_SHIFT) & MPIDR_AFFLVL_MASK; 30*91f16700Schasinglulu cpu_id = (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK; 31*91f16700Schasinglulu pe_id = (mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK; 32*91f16700Schasinglulu #else 33*91f16700Schasinglulu valid_mask = ~(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK); 34*91f16700Schasinglulu cluster_id = (unsigned int) ((mpidr >> MPIDR_AFF1_SHIFT) & 35*91f16700Schasinglulu MPIDR_AFFLVL_MASK); 36*91f16700Schasinglulu cpu_id = (unsigned int) ((mpidr >> MPIDR_AFF0_SHIFT) & 37*91f16700Schasinglulu MPIDR_AFFLVL_MASK); 38*91f16700Schasinglulu #endif /* ARM_PLAT_MT */ 39*91f16700Schasinglulu 40*91f16700Schasinglulu mpidr &= MPIDR_AFFINITY_MASK; 41*91f16700Schasinglulu if ((mpidr & valid_mask) != 0U) 42*91f16700Schasinglulu return -1; 43*91f16700Schasinglulu 44*91f16700Schasinglulu if (cluster_id >= PLAT_ARM_CLUSTER_COUNT) 45*91f16700Schasinglulu return -1; 46*91f16700Schasinglulu 47*91f16700Schasinglulu /* Validate cpu_id by checking whether it represents a CPU in 48*91f16700Schasinglulu one of the two clusters present on the platform. */ 49*91f16700Schasinglulu if (cpu_id >= plat_arm_get_cluster_core_count(mpidr)) 50*91f16700Schasinglulu return -1; 51*91f16700Schasinglulu 52*91f16700Schasinglulu #if ARM_PLAT_MT 53*91f16700Schasinglulu if (pe_id >= plat_arm_get_cpu_pe_count(mpidr)) 54*91f16700Schasinglulu return -1; 55*91f16700Schasinglulu #endif /* ARM_PLAT_MT */ 56*91f16700Schasinglulu 57*91f16700Schasinglulu return 0; 58*91f16700Schasinglulu } 59