1*91f16700Schasinglulu/* 2*91f16700Schasinglulu * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu#include <asm_macros.S> 7*91f16700Schasinglulu#include <platform_def.h> 8*91f16700Schasinglulu 9*91f16700Schasinglulu .weak plat_arm_calc_core_pos 10*91f16700Schasinglulu .weak plat_my_core_pos 11*91f16700Schasinglulu .globl plat_crash_console_init 12*91f16700Schasinglulu .globl plat_crash_console_putc 13*91f16700Schasinglulu .globl plat_crash_console_flush 14*91f16700Schasinglulu .globl platform_mem_init 15*91f16700Schasinglulu 16*91f16700Schasinglulu 17*91f16700Schasinglulu /* ----------------------------------------------------- 18*91f16700Schasinglulu * unsigned int plat_my_core_pos(void) 19*91f16700Schasinglulu * This function uses the plat_arm_calc_core_pos() 20*91f16700Schasinglulu * definition to get the index of the calling CPU. 21*91f16700Schasinglulu * ----------------------------------------------------- 22*91f16700Schasinglulu */ 23*91f16700Schasinglulufunc plat_my_core_pos 24*91f16700Schasinglulu mrs x0, mpidr_el1 25*91f16700Schasinglulu b plat_arm_calc_core_pos 26*91f16700Schasingluluendfunc plat_my_core_pos 27*91f16700Schasinglulu 28*91f16700Schasinglulu /* ----------------------------------------------------- 29*91f16700Schasinglulu * unsigned int plat_arm_calc_core_pos(u_register_t mpidr) 30*91f16700Schasinglulu * Helper function to calculate the core position. 31*91f16700Schasinglulu * With this function: CorePos = (ClusterId * 4) + 32*91f16700Schasinglulu * CoreId 33*91f16700Schasinglulu * ----------------------------------------------------- 34*91f16700Schasinglulu */ 35*91f16700Schasinglulufunc plat_arm_calc_core_pos 36*91f16700Schasinglulu and x1, x0, #MPIDR_CPU_MASK 37*91f16700Schasinglulu and x0, x0, #MPIDR_CLUSTER_MASK 38*91f16700Schasinglulu add x0, x1, x0, LSR #6 39*91f16700Schasinglulu ret 40*91f16700Schasingluluendfunc plat_arm_calc_core_pos 41*91f16700Schasinglulu 42*91f16700Schasinglulu /* --------------------------------------------- 43*91f16700Schasinglulu * int plat_crash_console_init(void) 44*91f16700Schasinglulu * Function to initialize the crash console 45*91f16700Schasinglulu * without a C Runtime to print crash report. 46*91f16700Schasinglulu * Clobber list : x0 - x4 47*91f16700Schasinglulu * --------------------------------------------- 48*91f16700Schasinglulu */ 49*91f16700Schasinglulufunc plat_crash_console_init 50*91f16700Schasinglulu mov_imm x0, PLAT_ARM_CRASH_UART_BASE 51*91f16700Schasinglulu mov_imm x1, PLAT_ARM_CRASH_UART_CLK_IN_HZ 52*91f16700Schasinglulu mov_imm x2, ARM_CONSOLE_BAUDRATE 53*91f16700Schasinglulu b console_pl011_core_init 54*91f16700Schasingluluendfunc plat_crash_console_init 55*91f16700Schasinglulu 56*91f16700Schasinglulu /* --------------------------------------------- 57*91f16700Schasinglulu * int plat_crash_console_putc(int c) 58*91f16700Schasinglulu * Function to print a character on the crash 59*91f16700Schasinglulu * console without a C Runtime. 60*91f16700Schasinglulu * Clobber list : x1, x2 61*91f16700Schasinglulu * --------------------------------------------- 62*91f16700Schasinglulu */ 63*91f16700Schasinglulufunc plat_crash_console_putc 64*91f16700Schasinglulu mov_imm x1, PLAT_ARM_CRASH_UART_BASE 65*91f16700Schasinglulu b console_pl011_core_putc 66*91f16700Schasingluluendfunc plat_crash_console_putc 67*91f16700Schasinglulu 68*91f16700Schasinglulu /* --------------------------------------------- 69*91f16700Schasinglulu * void plat_crash_console_flush() 70*91f16700Schasinglulu * Function to force a write of all buffered 71*91f16700Schasinglulu * data that hasn't been output. 72*91f16700Schasinglulu * Out : void. 73*91f16700Schasinglulu * Clobber list : r0 74*91f16700Schasinglulu * --------------------------------------------- 75*91f16700Schasinglulu */ 76*91f16700Schasinglulufunc plat_crash_console_flush 77*91f16700Schasinglulu mov_imm x0, PLAT_ARM_CRASH_UART_BASE 78*91f16700Schasinglulu b console_pl011_core_flush 79*91f16700Schasingluluendfunc plat_crash_console_flush 80*91f16700Schasinglulu 81*91f16700Schasinglulu /* --------------------------------------------------------------------- 82*91f16700Schasinglulu * We don't need to carry out any memory initialization on ARM 83*91f16700Schasinglulu * platforms. The Secure RAM is accessible straight away. 84*91f16700Schasinglulu * --------------------------------------------------------------------- 85*91f16700Schasinglulu */ 86*91f16700Schasinglulufunc platform_mem_init 87*91f16700Schasinglulu ret 88*91f16700Schasingluluendfunc platform_mem_init 89