1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #include <plat/arm/common/plat_arm.h> 8*91f16700Schasinglulu #include <plat/arm/css/common/css_pm.h> 9*91f16700Schasinglulu 10*91f16700Schasinglulu /****************************************************************************** 11*91f16700Schasinglulu * The power domain tree descriptor. 12*91f16700Schasinglulu ******************************************************************************/ 13*91f16700Schasinglulu const unsigned char tc_pd_tree_desc[] = { 14*91f16700Schasinglulu PLAT_ARM_CLUSTER_COUNT, 15*91f16700Schasinglulu PLAT_MAX_CPUS_PER_CLUSTER, 16*91f16700Schasinglulu }; 17*91f16700Schasinglulu 18*91f16700Schasinglulu /******************************************************************************* 19*91f16700Schasinglulu * This function returns the topology tree information. 20*91f16700Schasinglulu ******************************************************************************/ 21*91f16700Schasinglulu const unsigned char *plat_get_power_domain_tree_desc(void) 22*91f16700Schasinglulu { 23*91f16700Schasinglulu return tc_pd_tree_desc; 24*91f16700Schasinglulu } 25*91f16700Schasinglulu 26*91f16700Schasinglulu /******************************************************************************* 27*91f16700Schasinglulu * The array mapping platform core position (implemented by plat_my_core_pos()) 28*91f16700Schasinglulu * to the SCMI power domain ID implemented by SCP. 29*91f16700Schasinglulu ******************************************************************************/ 30*91f16700Schasinglulu const uint32_t plat_css_core_pos_to_scmi_dmn_id_map[] = { 31*91f16700Schasinglulu (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x0)), 32*91f16700Schasinglulu (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x1)), 33*91f16700Schasinglulu (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x2)), 34*91f16700Schasinglulu (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x3)), 35*91f16700Schasinglulu (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x4)), 36*91f16700Schasinglulu (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x5)), 37*91f16700Schasinglulu (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x6)), 38*91f16700Schasinglulu (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x7)), 39*91f16700Schasinglulu }; 40*91f16700Schasinglulu 41*91f16700Schasinglulu /******************************************************************************* 42*91f16700Schasinglulu * This function returns the core count within the cluster corresponding to 43*91f16700Schasinglulu * `mpidr`. 44*91f16700Schasinglulu ******************************************************************************/ 45*91f16700Schasinglulu unsigned int plat_arm_get_cluster_core_count(u_register_t mpidr) 46*91f16700Schasinglulu { 47*91f16700Schasinglulu return PLAT_MAX_CPUS_PER_CLUSTER; 48*91f16700Schasinglulu } 49*91f16700Schasinglulu 50*91f16700Schasinglulu #if ARM_PLAT_MT 51*91f16700Schasinglulu /****************************************************************************** 52*91f16700Schasinglulu * Return the number of PE's supported by the CPU. 53*91f16700Schasinglulu *****************************************************************************/ 54*91f16700Schasinglulu unsigned int plat_arm_get_cpu_pe_count(u_register_t mpidr) 55*91f16700Schasinglulu { 56*91f16700Schasinglulu return PLAT_MAX_PE_PER_CPU; 57*91f16700Schasinglulu } 58*91f16700Schasinglulu #endif 59