1*91f16700Schasinglulu/* 2*91f16700Schasinglulu * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu#include <arch.h> 8*91f16700Schasinglulu#include <asm_macros.S> 9*91f16700Schasinglulu#include <platform_def.h> 10*91f16700Schasinglulu#include <cpu_macros.S> 11*91f16700Schasinglulu 12*91f16700Schasinglulu .globl plat_arm_calc_core_pos 13*91f16700Schasinglulu .globl plat_reset_handler 14*91f16700Schasinglulu 15*91f16700Schasinglulu /* --------------------------------------------------------------------- 16*91f16700Schasinglulu * unsigned int plat_arm_calc_core_pos(u_register_t mpidr) 17*91f16700Schasinglulu * 18*91f16700Schasinglulu * Function to calculate the core position on TC. 19*91f16700Schasinglulu * 20*91f16700Schasinglulu * (ClusterId * PLAT_MAX_CPUS_PER_CLUSTER * PLAT_MAX_PE_PER_CPU) + 21*91f16700Schasinglulu * (CPUId * PLAT_MAX_PE_PER_CPU) + 22*91f16700Schasinglulu * ThreadId 23*91f16700Schasinglulu * 24*91f16700Schasinglulu * which can be simplified as: 25*91f16700Schasinglulu * 26*91f16700Schasinglulu * ((ClusterId * PLAT_MAX_CPUS_PER_CLUSTER + CPUId) * PLAT_MAX_PE_PER_CPU) 27*91f16700Schasinglulu * + ThreadId 28*91f16700Schasinglulu * --------------------------------------------------------------------- 29*91f16700Schasinglulu */ 30*91f16700Schasinglulufunc plat_arm_calc_core_pos 31*91f16700Schasinglulu /* 32*91f16700Schasinglulu * Check for MT bit in MPIDR. If not set, shift MPIDR to left to make it 33*91f16700Schasinglulu * look as if in a multi-threaded implementation. 34*91f16700Schasinglulu */ 35*91f16700Schasinglulu tst x0, #MPIDR_MT_MASK 36*91f16700Schasinglulu lsl x3, x0, #MPIDR_AFFINITY_BITS 37*91f16700Schasinglulu csel x3, x3, x0, eq 38*91f16700Schasinglulu 39*91f16700Schasinglulu /* Extract individual affinity fields from MPIDR */ 40*91f16700Schasinglulu ubfx x0, x3, #MPIDR_AFF0_SHIFT, #MPIDR_AFFINITY_BITS 41*91f16700Schasinglulu ubfx x1, x3, #MPIDR_AFF1_SHIFT, #MPIDR_AFFINITY_BITS 42*91f16700Schasinglulu ubfx x2, x3, #MPIDR_AFF2_SHIFT, #MPIDR_AFFINITY_BITS 43*91f16700Schasinglulu 44*91f16700Schasinglulu /* Compute linear position */ 45*91f16700Schasinglulu mov x4, #PLAT_MAX_CPUS_PER_CLUSTER 46*91f16700Schasinglulu madd x1, x2, x4, x1 47*91f16700Schasinglulu mov x5, #PLAT_MAX_PE_PER_CPU 48*91f16700Schasinglulu madd x0, x1, x5, x0 49*91f16700Schasinglulu ret 50*91f16700Schasingluluendfunc plat_arm_calc_core_pos 51*91f16700Schasinglulu 52*91f16700Schasinglulu /* ----------------------------------------------------- 53*91f16700Schasinglulu * void plat_reset_handler(void); 54*91f16700Schasinglulu * 55*91f16700Schasinglulu * Determine the CPU MIDR and disable power down bit for 56*91f16700Schasinglulu * that CPU. 57*91f16700Schasinglulu * ----------------------------------------------------- 58*91f16700Schasinglulu */ 59*91f16700Schasinglulufunc plat_reset_handler 60*91f16700Schasinglulu ret 61*91f16700Schasingluluendfunc plat_reset_handler 62