1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #include <plat/arm/common/plat_arm.h> 8*91f16700Schasinglulu #include <plat/arm/css/common/css_pm.h> 9*91f16700Schasinglulu 10*91f16700Schasinglulu /****************************************************************************** 11*91f16700Schasinglulu * The power domain tree descriptor. 12*91f16700Schasinglulu ******************************************************************************/ 13*91f16700Schasinglulu const unsigned char rd_v1_pd_tree_desc[] = { 14*91f16700Schasinglulu PLAT_ARM_CLUSTER_COUNT, 15*91f16700Schasinglulu CSS_SGI_MAX_CPUS_PER_CLUSTER, 16*91f16700Schasinglulu CSS_SGI_MAX_CPUS_PER_CLUSTER, 17*91f16700Schasinglulu CSS_SGI_MAX_CPUS_PER_CLUSTER, 18*91f16700Schasinglulu CSS_SGI_MAX_CPUS_PER_CLUSTER, 19*91f16700Schasinglulu CSS_SGI_MAX_CPUS_PER_CLUSTER, 20*91f16700Schasinglulu CSS_SGI_MAX_CPUS_PER_CLUSTER, 21*91f16700Schasinglulu CSS_SGI_MAX_CPUS_PER_CLUSTER, 22*91f16700Schasinglulu CSS_SGI_MAX_CPUS_PER_CLUSTER, 23*91f16700Schasinglulu CSS_SGI_MAX_CPUS_PER_CLUSTER, 24*91f16700Schasinglulu CSS_SGI_MAX_CPUS_PER_CLUSTER, 25*91f16700Schasinglulu CSS_SGI_MAX_CPUS_PER_CLUSTER, 26*91f16700Schasinglulu CSS_SGI_MAX_CPUS_PER_CLUSTER, 27*91f16700Schasinglulu CSS_SGI_MAX_CPUS_PER_CLUSTER, 28*91f16700Schasinglulu CSS_SGI_MAX_CPUS_PER_CLUSTER, 29*91f16700Schasinglulu CSS_SGI_MAX_CPUS_PER_CLUSTER, 30*91f16700Schasinglulu CSS_SGI_MAX_CPUS_PER_CLUSTER 31*91f16700Schasinglulu }; 32*91f16700Schasinglulu 33*91f16700Schasinglulu /******************************************************************************* 34*91f16700Schasinglulu * This function returns the topology tree information. 35*91f16700Schasinglulu ******************************************************************************/ 36*91f16700Schasinglulu const unsigned char *plat_get_power_domain_tree_desc(void) 37*91f16700Schasinglulu { 38*91f16700Schasinglulu return rd_v1_pd_tree_desc; 39*91f16700Schasinglulu } 40*91f16700Schasinglulu 41*91f16700Schasinglulu /******************************************************************************* 42*91f16700Schasinglulu * The array mapping platform core position (implemented by plat_my_core_pos()) 43*91f16700Schasinglulu * to the SCMI power domain ID implemented by SCP. 44*91f16700Schasinglulu ******************************************************************************/ 45*91f16700Schasinglulu const uint32_t plat_css_core_pos_to_scmi_dmn_id_map[] = { 46*91f16700Schasinglulu (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x0)), 47*91f16700Schasinglulu (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x1)), 48*91f16700Schasinglulu (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x2)), 49*91f16700Schasinglulu (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x3)), 50*91f16700Schasinglulu (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x4)), 51*91f16700Schasinglulu (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x5)), 52*91f16700Schasinglulu (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x6)), 53*91f16700Schasinglulu (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x7)), 54*91f16700Schasinglulu (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x8)), 55*91f16700Schasinglulu (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x9)), 56*91f16700Schasinglulu (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0xA)), 57*91f16700Schasinglulu (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0xB)), 58*91f16700Schasinglulu (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0xC)), 59*91f16700Schasinglulu (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0xD)), 60*91f16700Schasinglulu (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0xE)), 61*91f16700Schasinglulu (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0xF)) 62*91f16700Schasinglulu }; 63