1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2020-2022, ARM Limited and Contributors. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #ifndef PLATFORM_DEF_H 8*91f16700Schasinglulu #define PLATFORM_DEF_H 9*91f16700Schasinglulu 10*91f16700Schasinglulu #include <lib/utils_def.h> 11*91f16700Schasinglulu 12*91f16700Schasinglulu #include <sgi_soc_platform_def.h> 13*91f16700Schasinglulu 14*91f16700Schasinglulu #define PLAT_ARM_CLUSTER_COUNT U(16) 15*91f16700Schasinglulu #define CSS_SGI_MAX_CPUS_PER_CLUSTER U(1) 16*91f16700Schasinglulu #define CSS_SGI_MAX_PE_PER_CPU U(1) 17*91f16700Schasinglulu 18*91f16700Schasinglulu #define PLAT_CSS_MHU_BASE UL(0x45400000) 19*91f16700Schasinglulu #define PLAT_MHUV2_BASE PLAT_CSS_MHU_BASE 20*91f16700Schasinglulu 21*91f16700Schasinglulu #define CSS_SYSTEM_PWR_DMN_LVL ARM_PWR_LVL2 22*91f16700Schasinglulu #define PLAT_MAX_PWR_LVL ARM_PWR_LVL1 23*91f16700Schasinglulu 24*91f16700Schasinglulu /* TZC Related Constants */ 25*91f16700Schasinglulu #define PLAT_ARM_TZC_BASE UL(0x21830000) 26*91f16700Schasinglulu #define PLAT_ARM_TZC_FILTERS TZC_400_REGION_ATTR_FILTER_BIT(0) 27*91f16700Schasinglulu 28*91f16700Schasinglulu #define TZC400_OFFSET UL(0x1000000) 29*91f16700Schasinglulu #define TZC400_COUNT 4 30*91f16700Schasinglulu 31*91f16700Schasinglulu #define TZC400_BASE(n) (PLAT_ARM_TZC_BASE + \ 32*91f16700Schasinglulu (n * TZC400_OFFSET)) 33*91f16700Schasinglulu 34*91f16700Schasinglulu #define TZC_NSAID_ALL_AP U(0) 35*91f16700Schasinglulu #define TZC_NSAID_PCI U(1) 36*91f16700Schasinglulu #define TZC_NSAID_HDLCD0 U(2) 37*91f16700Schasinglulu #define TZC_NSAID_CLCD U(7) 38*91f16700Schasinglulu #define TZC_NSAID_AP U(9) 39*91f16700Schasinglulu #define TZC_NSAID_VIRTIO U(15) 40*91f16700Schasinglulu 41*91f16700Schasinglulu #define PLAT_ARM_TZC_NS_DEV_ACCESS \ 42*91f16700Schasinglulu (TZC_REGION_ACCESS_RDWR(TZC_NSAID_ALL_AP)) | \ 43*91f16700Schasinglulu (TZC_REGION_ACCESS_RDWR(TZC_NSAID_HDLCD0)) | \ 44*91f16700Schasinglulu (TZC_REGION_ACCESS_RDWR(TZC_NSAID_PCI)) | \ 45*91f16700Schasinglulu (TZC_REGION_ACCESS_RDWR(TZC_NSAID_AP)) | \ 46*91f16700Schasinglulu (TZC_REGION_ACCESS_RDWR(TZC_NSAID_CLCD)) | \ 47*91f16700Schasinglulu (TZC_REGION_ACCESS_RDWR(TZC_NSAID_VIRTIO)) 48*91f16700Schasinglulu 49*91f16700Schasinglulu /* Maximum number of address bits used per chip */ 50*91f16700Schasinglulu #define CSS_SGI_ADDR_BITS_PER_CHIP U(42) 51*91f16700Schasinglulu 52*91f16700Schasinglulu /* 53*91f16700Schasinglulu * Physical and virtual address space limits for MMU in AARCH64 & AARCH32 modes 54*91f16700Schasinglulu */ 55*91f16700Schasinglulu #ifdef __aarch64__ 56*91f16700Schasinglulu #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << CSS_SGI_ADDR_BITS_PER_CHIP) 57*91f16700Schasinglulu #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << CSS_SGI_ADDR_BITS_PER_CHIP) 58*91f16700Schasinglulu #else 59*91f16700Schasinglulu #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) 60*91f16700Schasinglulu #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) 61*91f16700Schasinglulu #endif 62*91f16700Schasinglulu 63*91f16700Schasinglulu /* GIC related constants */ 64*91f16700Schasinglulu #define PLAT_ARM_GICD_BASE UL(0x30000000) 65*91f16700Schasinglulu #define PLAT_ARM_GICC_BASE UL(0x2C000000) 66*91f16700Schasinglulu #define PLAT_ARM_GICR_BASE UL(0x30140000) 67*91f16700Schasinglulu 68*91f16700Schasinglulu #endif /* PLATFORM_DEF_H */ 69