1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2020-2023, ARM Limited and Contributors. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #include <plat/arm/common/plat_arm.h> 8*91f16700Schasinglulu #include <plat/arm/css/common/css_pm.h> 9*91f16700Schasinglulu 10*91f16700Schasinglulu /****************************************************************************** 11*91f16700Schasinglulu * The power domain tree descriptor. 12*91f16700Schasinglulu ******************************************************************************/ 13*91f16700Schasinglulu const unsigned char rd_n2_pd_tree_desc[] = { 14*91f16700Schasinglulu (PLAT_ARM_CLUSTER_COUNT) * (CSS_SGI_CHIP_COUNT), 15*91f16700Schasinglulu CSS_SGI_MAX_CPUS_PER_CLUSTER, 16*91f16700Schasinglulu CSS_SGI_MAX_CPUS_PER_CLUSTER, 17*91f16700Schasinglulu CSS_SGI_MAX_CPUS_PER_CLUSTER, 18*91f16700Schasinglulu CSS_SGI_MAX_CPUS_PER_CLUSTER, 19*91f16700Schasinglulu #if (PLAT_ARM_CLUSTER_COUNT > 4 || \ 20*91f16700Schasinglulu (CSS_SGI_PLATFORM_VARIANT == 2 && CSS_SGI_CHIP_COUNT > 1)) 21*91f16700Schasinglulu CSS_SGI_MAX_CPUS_PER_CLUSTER, 22*91f16700Schasinglulu CSS_SGI_MAX_CPUS_PER_CLUSTER, 23*91f16700Schasinglulu CSS_SGI_MAX_CPUS_PER_CLUSTER, 24*91f16700Schasinglulu CSS_SGI_MAX_CPUS_PER_CLUSTER, 25*91f16700Schasinglulu #endif 26*91f16700Schasinglulu #if (PLAT_ARM_CLUSTER_COUNT > 8 || \ 27*91f16700Schasinglulu (CSS_SGI_PLATFORM_VARIANT == 2 && CSS_SGI_CHIP_COUNT > 2)) 28*91f16700Schasinglulu CSS_SGI_MAX_CPUS_PER_CLUSTER, 29*91f16700Schasinglulu CSS_SGI_MAX_CPUS_PER_CLUSTER, 30*91f16700Schasinglulu CSS_SGI_MAX_CPUS_PER_CLUSTER, 31*91f16700Schasinglulu CSS_SGI_MAX_CPUS_PER_CLUSTER, 32*91f16700Schasinglulu #endif 33*91f16700Schasinglulu #if (PLAT_ARM_CLUSTER_COUNT > 8 || \ 34*91f16700Schasinglulu (CSS_SGI_PLATFORM_VARIANT == 2 && CSS_SGI_CHIP_COUNT > 3)) 35*91f16700Schasinglulu CSS_SGI_MAX_CPUS_PER_CLUSTER, 36*91f16700Schasinglulu CSS_SGI_MAX_CPUS_PER_CLUSTER, 37*91f16700Schasinglulu CSS_SGI_MAX_CPUS_PER_CLUSTER, 38*91f16700Schasinglulu CSS_SGI_MAX_CPUS_PER_CLUSTER, 39*91f16700Schasinglulu #endif 40*91f16700Schasinglulu }; 41*91f16700Schasinglulu 42*91f16700Schasinglulu /******************************************************************************* 43*91f16700Schasinglulu * This function returns the topology tree information. 44*91f16700Schasinglulu ******************************************************************************/ 45*91f16700Schasinglulu const unsigned char *plat_get_power_domain_tree_desc(void) 46*91f16700Schasinglulu { 47*91f16700Schasinglulu return rd_n2_pd_tree_desc; 48*91f16700Schasinglulu } 49*91f16700Schasinglulu 50*91f16700Schasinglulu /******************************************************************************* 51*91f16700Schasinglulu * The array mapping platform core position (implemented by plat_my_core_pos()) 52*91f16700Schasinglulu * to the SCMI power domain ID implemented by SCP. 53*91f16700Schasinglulu ******************************************************************************/ 54*91f16700Schasinglulu #if (CSS_SGI_PLATFORM_VARIANT == 2) 55*91f16700Schasinglulu const uint32_t plat_css_core_pos_to_scmi_dmn_id_map[] = { 56*91f16700Schasinglulu (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x0)), 57*91f16700Schasinglulu (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x1)), 58*91f16700Schasinglulu (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x2)), 59*91f16700Schasinglulu (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x3)), 60*91f16700Schasinglulu #if (CSS_SGI_CHIP_COUNT > 1) 61*91f16700Schasinglulu (SET_SCMI_CHANNEL_ID(0x1) | SET_SCMI_DOMAIN_ID(0x0)), 62*91f16700Schasinglulu (SET_SCMI_CHANNEL_ID(0x1) | SET_SCMI_DOMAIN_ID(0x1)), 63*91f16700Schasinglulu (SET_SCMI_CHANNEL_ID(0x1) | SET_SCMI_DOMAIN_ID(0x2)), 64*91f16700Schasinglulu (SET_SCMI_CHANNEL_ID(0x1) | SET_SCMI_DOMAIN_ID(0x3)), 65*91f16700Schasinglulu #endif 66*91f16700Schasinglulu #if (CSS_SGI_CHIP_COUNT > 2) 67*91f16700Schasinglulu (SET_SCMI_CHANNEL_ID(0x2) | SET_SCMI_DOMAIN_ID(0x0)), 68*91f16700Schasinglulu (SET_SCMI_CHANNEL_ID(0x2) | SET_SCMI_DOMAIN_ID(0x1)), 69*91f16700Schasinglulu (SET_SCMI_CHANNEL_ID(0x2) | SET_SCMI_DOMAIN_ID(0x2)), 70*91f16700Schasinglulu (SET_SCMI_CHANNEL_ID(0x2) | SET_SCMI_DOMAIN_ID(0x3)), 71*91f16700Schasinglulu #endif 72*91f16700Schasinglulu #if (CSS_SGI_CHIP_COUNT > 3) 73*91f16700Schasinglulu (SET_SCMI_CHANNEL_ID(0x3) | SET_SCMI_DOMAIN_ID(0x0)), 74*91f16700Schasinglulu (SET_SCMI_CHANNEL_ID(0x3) | SET_SCMI_DOMAIN_ID(0x1)), 75*91f16700Schasinglulu (SET_SCMI_CHANNEL_ID(0x3) | SET_SCMI_DOMAIN_ID(0x2)), 76*91f16700Schasinglulu (SET_SCMI_CHANNEL_ID(0x3) | SET_SCMI_DOMAIN_ID(0x3)), 77*91f16700Schasinglulu #endif 78*91f16700Schasinglulu }; 79*91f16700Schasinglulu #else 80*91f16700Schasinglulu const uint32_t plat_css_core_pos_to_scmi_dmn_id_map[] = { 81*91f16700Schasinglulu (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x0)), 82*91f16700Schasinglulu (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x1)), 83*91f16700Schasinglulu (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x2)), 84*91f16700Schasinglulu (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x3)), 85*91f16700Schasinglulu (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x4)), 86*91f16700Schasinglulu (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x5)), 87*91f16700Schasinglulu (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x6)), 88*91f16700Schasinglulu (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x7)), 89*91f16700Schasinglulu #if (PLAT_ARM_CLUSTER_COUNT > 8) 90*91f16700Schasinglulu (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x8)), 91*91f16700Schasinglulu (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x9)), 92*91f16700Schasinglulu (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0xA)), 93*91f16700Schasinglulu (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0xB)), 94*91f16700Schasinglulu (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0xC)), 95*91f16700Schasinglulu (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0xD)), 96*91f16700Schasinglulu (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0xE)), 97*91f16700Schasinglulu (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0xF)), 98*91f16700Schasinglulu #endif 99*91f16700Schasinglulu }; 100*91f16700Schasinglulu #endif 101