1*91f16700Schasinglulu /* 2*91f16700Schasinglulu * Copyright (c) 2020-2021, ARM Limited and Contributors. All rights reserved. 3*91f16700Schasinglulu * 4*91f16700Schasinglulu * SPDX-License-Identifier: BSD-3-Clause 5*91f16700Schasinglulu */ 6*91f16700Schasinglulu 7*91f16700Schasinglulu #include <common/debug.h> 8*91f16700Schasinglulu #include <plat/arm/common/plat_arm.h> 9*91f16700Schasinglulu #include <platform_def.h> 10*91f16700Schasinglulu 11*91f16700Schasinglulu #define RDN2_TZC_CPER_REGION \ 12*91f16700Schasinglulu {CSS_SGI_SP_CPER_BUF_BASE, (CSS_SGI_SP_CPER_BUF_BASE + \ 13*91f16700Schasinglulu CSS_SGI_SP_CPER_BUF_SIZE) - 1, TZC_REGION_S_NONE, \ 14*91f16700Schasinglulu PLAT_ARM_TZC_NS_DEV_ACCESS} 15*91f16700Schasinglulu 16*91f16700Schasinglulu static const arm_tzc_regions_info_t tzc_regions[] = { 17*91f16700Schasinglulu ARM_TZC_REGIONS_DEF, 18*91f16700Schasinglulu #if ENABLE_FEAT_RAS && FFH_SUPPORT 19*91f16700Schasinglulu RDN2_TZC_CPER_REGION, 20*91f16700Schasinglulu #endif 21*91f16700Schasinglulu {} 22*91f16700Schasinglulu }; 23*91f16700Schasinglulu 24*91f16700Schasinglulu #if (CSS_SGI_PLATFORM_VARIANT == 2 && CSS_SGI_CHIP_COUNT > 1) 25*91f16700Schasinglulu static const arm_tzc_regions_info_t tzc_regions_mc[][CSS_SGI_CHIP_COUNT - 1] = { 26*91f16700Schasinglulu { 27*91f16700Schasinglulu /* TZC memory regions for second chip */ 28*91f16700Schasinglulu SGI_PLAT_TZC_NS_REMOTE_REGIONS_DEF(1), 29*91f16700Schasinglulu {} 30*91f16700Schasinglulu }, 31*91f16700Schasinglulu #if CSS_SGI_CHIP_COUNT > 2 32*91f16700Schasinglulu { 33*91f16700Schasinglulu /* TZC memory regions for third chip */ 34*91f16700Schasinglulu SGI_PLAT_TZC_NS_REMOTE_REGIONS_DEF(2), 35*91f16700Schasinglulu {} 36*91f16700Schasinglulu }, 37*91f16700Schasinglulu #endif 38*91f16700Schasinglulu #if CSS_SGI_CHIP_COUNT > 3 39*91f16700Schasinglulu { 40*91f16700Schasinglulu /* TZC memory regions for fourth chip */ 41*91f16700Schasinglulu SGI_PLAT_TZC_NS_REMOTE_REGIONS_DEF(3), 42*91f16700Schasinglulu {} 43*91f16700Schasinglulu }, 44*91f16700Schasinglulu #endif 45*91f16700Schasinglulu }; 46*91f16700Schasinglulu #endif /* CSS_SGI_PLATFORM_VARIANT && CSS_SGI_CHIP_COUNT */ 47*91f16700Schasinglulu 48*91f16700Schasinglulu /* Initialize the secure environment */ 49*91f16700Schasinglulu void plat_arm_security_setup(void) 50*91f16700Schasinglulu { 51*91f16700Schasinglulu unsigned int i; 52*91f16700Schasinglulu 53*91f16700Schasinglulu INFO("Configuring TrustZone Controller for Chip 0\n"); 54*91f16700Schasinglulu 55*91f16700Schasinglulu for (i = 0; i < TZC400_COUNT; i++) { 56*91f16700Schasinglulu arm_tzc400_setup(TZC400_BASE(i), tzc_regions); 57*91f16700Schasinglulu } 58*91f16700Schasinglulu 59*91f16700Schasinglulu #if (CSS_SGI_PLATFORM_VARIANT == 2 && CSS_SGI_CHIP_COUNT > 1) 60*91f16700Schasinglulu unsigned int j; 61*91f16700Schasinglulu 62*91f16700Schasinglulu for (i = 1; i < CSS_SGI_CHIP_COUNT; i++) { 63*91f16700Schasinglulu INFO("Configuring TrustZone Controller for Chip %u\n", i); 64*91f16700Schasinglulu 65*91f16700Schasinglulu for (j = 0; j < TZC400_COUNT; j++) { 66*91f16700Schasinglulu arm_tzc400_setup(CSS_SGI_REMOTE_CHIP_MEM_OFFSET(i) 67*91f16700Schasinglulu + TZC400_BASE(j), tzc_regions_mc[i-1]); 68*91f16700Schasinglulu } 69*91f16700Schasinglulu } 70*91f16700Schasinglulu #endif 71*91f16700Schasinglulu } 72